Suspended Fin Channel Structure for Gate-All-Around Transistors
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Solution Overview
Problem
The manufacturing of fin semiconductor devices with suspended fin channels and gate-all-around structures is complex and costly, making it challenging to achieve high performance and suppress short channel effects and electric leakage.
Innovation Solution
A method involving epitaxial growth and oxidation of fin channels to form a suspended structure over a substrate, followed by the formation of a gate-all-around structure, simplifying the process and reducing costs while enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar manufacturing technologies are used, then the manufacturing process is simple, but the device performance deteriorates due to short channel effects and electric leakage
Solution Approach 1:
The patent transitions from planar 2D transistor structures to 3D FinFET structures with vertical fins extending from the substrate. This dimensional change creates a non-planar surface that improves gate control over the channel while maintaining compatibility with standard semiconductor manufacturing processes, thereby enhancing device performance without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent implements a nested structure where the gate electrode wraps around the fin channel in a gate-all-around configuration. This nesting of the gate structure around the channel provides superior electrostatic control and suppresses short channel effects, improving device reliability while using established fabrication techniques
2Reliability
If gate-all-around structures are implemented, then short channel effects are suppressed, but the manufacturing process becomes more complex
Solution Approach 1:
The patent performs preliminary actions by first forming the fin channel structure and sacrificial oxide layers before creating the gate electrode. This sequence allows the gate to be deposited around pre-formed structures, simplifying the overall process compared to attempting to form the gate first and then surround it with channel structures
Solution Approach 2:
The patent uses sacrificial oxide layers as intermediary structures during fabrication. These oxide layers are deposited and patterned to define fin regions, then selectively removed to release and suspend the fin channels. This intermediary approach enables complex 3D structures to be formed using standard planar deposition and etching processes
3Productivity
If device sizes are continuously decreased, then integration level increases, but manufacturing becomes increasingly challenging
Solution Approach 1:
The patent changes the geometric parameters of the transistor structure by creating vertical fins with controlled heights and widths. This parameter change allows continued scaling of device dimensions while maintaining effective gate control through the three-dimensional FinFET structure, enabling higher integration without proportionally increasing manufacturing difficulty
Solution Approach 2:
By transitioning to vertical fin structures, the patent exploits the third dimension (height) to maintain effective channel control as lateral dimensions are scaled down. This allows continued device miniaturization and higher integration levels while using modified versions of existing manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method allows for the formation of a fin semiconductor device with a suspended fin channel and all-around gate, effectively suppressing short channel effects and electric leakage, thereby improving device performance without additional manufacturing costs.
Implementation Method 1
epitaxially growing a top part of the fin channel base and extending the top part of the fin channel base sideways and upward to form a fin channel core
Implementation Method 2
oxidizing the fin channel base to form a fin channel structure, wherein the fin channel structure comprises the fin channel core surrounded with an oxide layer
Data Source
AI summary
A manufacturing method of a fin semiconductor device comprises: providing a substrate, wherein a fin channel base is patterned on and in contact with the substrate; epitaxially growing a top part of the fin channel base and extending the top part of the fin channel base sideways and upward to form a fin channel core; oxidizing the fin channel base to form a fin channel structure, wherein the fin channel structure comprises the fin channel core surrounded with an oxide layer at the top part of the fin channel base and an intermediate part of the fin channel base under the top part; and removing the oxide layer to expose the fin channel core, wherein the fin channel core suspends over the substrate.