Switch Metal-Line Layout for Lower Parasitic Inductance
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Solution Overview
Problem
Conventional buck switching regulators face limitations due to parasitic inductance issues, which restrict the slew rate of upper gate switches, primarily caused by the close proximity of metal lines leading to parallel and adjacent configurations that enhance manufacturing efficiency but increase parasitic inductance.
Innovation Solution
The design incorporates a semiconductor switch with strategically arranged top metal lines, where currents flow in opposite directions through adjacent and parallel metal lines, effectively canceling out parasitic inductance, thereby reducing total parasitic inductance and improving the slew rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal lines are arranged adjacent and close to each other to reduce switch size, then manufacturing cost is reduced and operation efficiency is enhanced, but parasitic inductance increases and slew rate is limited
Solution Approach 1:
The patent applies the inversion principle by reversing the current flow direction in one of the parallel metal lines. Specifically, the fourth metal line is configured so that current flows in the opposite direction compared to the third metal line, which causes the magnetic fields and parasitic inductances to cancel each other out. This allows the metal lines to be placed adjacent to each other for compactness while eliminating the harmful parasitic inductance effect.
Solution Approach 2:
The patent converts the harmful parasitic inductance generated by adjacent metal lines into a beneficial effect by strategically arranging current paths. The opposite-direction current flow in the fourth metal line transforms the previously harmful inductive coupling into a useful cancellation effect, where the parasitic inductances of adjacent lines neutralize each other, improving slew rate while maintaining compact layout.
2Area of stationary object
If metal lines are placed parallel and adjacent to reduce device area, then area is reduced, but parasitic inductance accumulates and limits performance
Solution Approach 1:
The patent applies the inversion principle by reversing the current flow direction in the fourth metal line relative to the third metal line. This configuration causes the magnetic fields generated by adjacent parallel lines to oppose each other, resulting in cancellation of parasitic inductance. The opposite current direction transforms the inductive coupling that would normally accumulate into a beneficial cancellation effect.
Solution Approach 2:
The patent converts the harmful parasitic inductance that naturally arises from parallel adjacent metal lines into a beneficial cancellation effect. By configuring the fourth metal line to carry current in the opposite direction, the previously harmful inductive effects are transformed into useful field cancellation, allowing compact parallel arrangement without performance degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces parasitic inductance, enhancing the operational efficiency and slew rate of the switch by ensuring that parasitic inductances generated by different current paths counteract each other, leading to improved performance in switching regulators.
Implementation Method 1
according to Ampere's circuital law, when the upper gate switch 11 is ON, because the input current Iin flowing through the metal line 121 and the inductor current IL flowing through the metal line 124 (which is in parallel to the metal line 121) flow along the same direction
Data Source
AI summary
A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.