Level Shifter Switch Module for Lower Delay and Static Current
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Solution Overview
Problem
Level shifters in semiconductor devices experience delays and increased power consumption due to the number of transistors involved in signal traversal and static current buildup, especially when operating in voltage domains with low gate-source voltages.
Innovation Solution
A semiconductor device design that includes a level shifter and a switch module, where the switch controller determines the relative voltages and generates control signals to bypass the level shifter when the input voltage is higher, reducing signal delay and static current by disconnecting the level shifter from the output and connecting the input directly to the output in such cases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the level shifter is used to shift signals between voltage domains, then voltage domain compatibility is improved, but signal delay increases
Solution Approach 1:
The patent implements a dynamic switching mechanism that adjusts the signal path based on voltage domain conditions. The switch module dynamically connects or disconnects the level shifter from the signal path, transitioning between two operational states: one where the level shifter is active for voltage domain conversion, and another where it is bypassed for direct signal transmission. This dynamic adaptation resolves the contradiction by making the system flexible enough to prioritize either voltage compatibility or signal speed depending on real-time conditions.
Solution Approach 2:
The patent segments the signal path into multiple routes: a level shifter path for voltage domain conversion and a direct path for fast signal transmission. The switch module acts as a router that directs signals through the appropriate segment based on voltage domain requirements. This segmentation allows the system to maintain both voltage domain compatibility and low signal delay by choosing the optimal path for each signaling event.
2Use of energy by moving object
If the level shifter operates in voltage domains with low gate-source voltages, then lower voltage operation is achieved, but power consumption increases
Solution Approach 1:
The patent employs periodic evaluation of voltage domain conditions through the voltage domain detection circuit, which continuously monitors and determines when voltage domain conversion is necessary. Based on this periodic assessment, the switch module alternates between engaging the level shifter for voltage conversion and bypassing it for direct transmission. This periodic activation pattern ensures the level shifter operates only when necessary, minimizing static current buildup and reducing overall power consumption while maintaining lower voltage operation capabilities.
3Reliability
If the level shifter is always connected in the signal path, then voltage domain conversion is ensured, but static current buildup occurs
Solution Approach 1:
The patent extracts the level shifter from the permanent signal path by introducing a switch module that can disconnect it when not needed. The switch module effectively removes the level shifter from the active circuit when voltage domain conversion is unnecessary, preventing static current buildup in the level shifter's transistor structures. This extraction approach maintains voltage domain conversion reliability by keeping the level shifter available when needed while eliminating its harmful static current effects during direct transmission modes.
Data Source
AI summary
A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.


