Switched-Capacitor Harmonic Rejection Mixer for Third-Order Suppression
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Solution Overview
Problem
Conventional harmonic rejection mixers face challenges in suppressing third-order harmonics, leading to significant spectrum regrowth outside the channel, which is particularly stringent in applications like 802.11ah, due to their complexity and high power consumption.
Innovation Solution
A switched capacitor based harmonic rejection mixer using clocks with two different duty cycles for phase control, employing 2-vector modulation to minimize third-order harmonics, reducing complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional harmonic rejection mixers are used, then third-order harmonics can be suppressed, but device complexity and power consumption increase
Solution Approach 1:
The patent changes the duty cycle parameter of the local oscillator signals from the conventional 50% to asymmetric values (25% and 75%). This parameter modification enables effective third-order harmonic suppression through the switched capacitor circuit while maintaining a simpler architecture compared to conventional harmonic rejection mixers that would require additional filtering stages or more complex LO signal generation
2Object-generated harmful factors
If conventional harmonic rejection mixers are used, then third-order harmonics can be suppressed, but power consumption increases
Solution Approach 1:
By modifying the duty cycle parameter to asymmetric values and using switched capacitor circuits, the patent achieves harmonic suppression through capacitive switching rather than requiring additional active filtering components. This approach reduces power consumption compared to conventional mixers that would need extra amplifiers or filters to achieve the same harmonic rejection
Solution Approach 2:
The patent replaces what would traditionally require complex analog filtering mechanisms with a switched capacitor implementation controlled by asymmetric duty cycle signals. This substitution uses digital-like switching control to achieve harmonic rejection, reducing the need for power-hungry analog filtering stages
3Productivity
If square wave LO signal is used, then up-conversion mixing is achieved, but high-order harmonics are generated causing spectrum regrowth
Solution Approach 1:
The patent changes the LO signal parameter from a simple square wave to asymmetric duty cycle waveforms (25%/75%). This modification maintains the strong fundamental component needed for efficient up-conversion while altering the harmonic spectrum to enable cancellation of third-order harmonics through the switched capacitor circuit's differential operation
Solution Approach 2:
The patent converts the inherently present high-order harmonics of the square wave LO signal into a beneficial cancellation mechanism. By using asymmetric duty cycle signals in the switched capacitor circuit, the third-order harmonics that would normally cause spectrum regrowth are transformed into canceling signals that suppress the harmful emissions
Data Source
AI summary
A harmonic rejection mixer that uses switched capacitors for amplitude control and uses two different duty cycle local oscillator (LO) signals for phase control for each harmonic. The harmonic rejection mixer uses 2-vector variable duty harmonic rejection. which allows for the harmonic rejection mixer to be less complex. consume less power, and/or use less components/space compared to conventional harmonic rejection mixers.