Switched Capacitor Power Circuit Well Biasing Against BOX Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing switched capacitor power source circuits face efficiency losses due to BOX capacitance when integrated into integrated circuits, and adding an n-Buried layer to counter this issue increases circuit area and manufacturing costs.
Innovation Solution
Connecting the well layer under capacitance elements in the integrated circuit to a potential point lower than the semiconductor substrate via a load circuit, such as a resistance element, reduces the effect of BOX capacitance and maintains efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If an n-Buried layer is added to counter BOX capacitance, then power conversion efficiency is improved, but circuit area and manufacturing costs increase
Solution Approach 1:
The patent introduces a load circuit as an intermediary element connected between the well layer and a potential point lower than the semiconductor substrate. This load circuit acts as a mediator to reduce the BOX capacitance effect without requiring structural modifications like adding an n-Buried layer, thereby maintaining power conversion efficiency while avoiding increased circuit area
Solution Approach 2:
The patent changes the electrical parameter (potential) of the well layer by connecting it to a potential point lower than the semiconductor substrate through the load circuit. This parameter change reduces the voltage difference across the BOX capacitance, thereby reducing its harmful effect on power conversion efficiency without increasing circuit area
2Loss of energy
If an n-Buried layer is added to counter BOX capacitance, then power conversion efficiency is improved, but manufacturing costs increase
Solution Approach 1:
The load circuit serves as an intermediary that achieves the desired effect (reducing BOX capacitance impact) through electrical connection rather than requiring additional semiconductor processing steps like n-Buried layer formation, thereby reducing manufacturing complexity and costs
Solution Approach 2:
The patent uses a simple load circuit (resistance element) that can be easily manufactured and integrated, replacing the need for complex and expensive n-Buried layer processing. The load circuit achieves the same functional goal at lower manufacturing cost
3Loss of energy
If the well layer is connected to a potential point lower than the semiconductor substrate via a load circuit, then power conversion efficiency is enhanced, but circuit complexity increases
Solution Approach 1:
The load circuit performs multiple functions: it reduces the BOX capacitance effect, sets the well layer potential, and provides a reference potential connection. By making this single element multi-functional, the patent avoids increasing overall circuit complexity while achieving improved power conversion efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances power conversion efficiency by reducing the impedance of the well layer, preventing efficiency loss and minimizing circuit area and manufacturing costs.
Implementation Method 1
When a switched capacitor power source circuit is configured as an integrated circuit, a so-called BOX capacitance is generated as a capacitive component in a BOX (i.e., Buried-Oxide) layer located below the capacitance element
Implementation Method 2
Connecting the well layer under capacitance elements in the integrated circuit to a potential point lower than the semiconductor substrate via a load circuit, such as a resistance element, reduces the effect of BOX capacitance
Data Source
AI summary
A switched capacitor power source circuit includes: an integrated circuit for converting an input voltage into a predetermined output voltage by charging and discharging a plurality of capacitance elements via a plurality of switching elements using a plurality of clock signals with different phases. A well layer disposed under each of the capacitance elements is connected via a load circuit to a point of potential equal to or lower than a potential of a semiconductor substrate constituting the integrated circuit.