Switched Integrator Circuit for Low-Error Delta-Sigma Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
State-of-the-art integrator circuits in delta sigma converters suffer from parasitic capacitance-induced charge errors due to voltage swings, leading to error currents that are not effectively mitigated by reducing clock frequency or using cascode switching, especially in low supply voltage implementations.
Innovation Solution
The integration circuit operates in multiple subphases, swapping the roles of amplifiers and capacitor connections to form inverting and dummy integrators, reducing voltage swings and charge errors through continuous integration and matching virtual ground voltages, eliminating the need for increased supply voltage or reduced clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the frequency of clock signal is reduced to reduce error contribution from charge packages, then measurement precision is improved, but conversion time increases and power consumption increases
Solution Approach 1:
The dummy amplifier is activated during idle phases to preliminarily charge the parasitic capacitances to the reference voltage, so that when the amplifier switches between integration phases, the voltage swings are minimized and charge errors are reduced without requiring lower clock frequencies
Solution Approach 2:
A dummy amplifier is introduced as an intermediary component that handles the idle current and charges the parasitic capacitances during non-integration phases, isolating the main amplifier from voltage swing-induced errors and allowing high-frequency operation without precision loss
2Measurement precision
If cascode switching scheme is introduced to reduce voltage swing, then measurement precision is improved, but device complexity increases and headroom requirements increase
Solution Approach 1:
A dummy amplifier is created as a copy of the main amplifier's input stage, which replicates the virtual ground behavior during idle phases. This copying approach simplifies the switching scheme compared to cascode structures while achieving similar voltage swing reduction and error mitigation
3Measurement precision
If cascode switching scheme is used to reduce voltage swing, then measurement precision is improved, but adaptability to low supply voltage decreases
Solution Approach 1:
The dummy amplifier copy requires minimal headroom compared to cascode structures, enabling the circuit to operate effectively in low supply voltage environments while still reducing voltage swings and improving measurement precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces residual errors and voltage swings, enabling faster conversion times and lower power consumption in delta sigma converters, particularly in temperature sensor applications.
Implementation Method 1
an amplifier A with a capacitance C coupled in the amplifier's feedback loop such that amplifier A and capacitance C form an inverting integrator
Implementation Method 2
A parasitic capacitance Cp1, Cp2 builds up at each input which receives the first or the second current I1, I2
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C~3D
AI summary
In an embodiment an integration circuit has a first input terminal (In1) configured to receive a first input signal (I1), a second input terminal (In2) configured to receive a second input signal (12), an output terminal (Out) to provide an output signal (Vout) as a function of the first and the second input signal (I1, 12), a first and a second amplifier (A1, A2), each being switchably connected between the first or the second input terminal (In1, In2) and the output terminal (Out), and a capacitor (C) which is switchably coupled in a feedback loop either of the first or of the second amplifier (A1, A2) such that the capacitor (C) and one of the first and the second amplifier (A1, A2) form an inverting integrator (Int) providing the output signal (Vout). Therein the integration circuit is prepared to be operated in a first and a second subphase, wherein in each of first and second subphases one of the first and the second input signals (I1, 12) is supplied to the inverting integrator (Int) and the respective other one of first and the second input signals (I1, 12) is supplied to the respective other one of the first and the second amplifier (A1, A2).