Switching Amplifier Bias Circuit for Pulse Width Distortion Cancellation
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Solution Overview
Problem
Class-D power amplifiers face issues with harmonics exceeding out-of-band spurious emission limits due to mismatched rise and fall times, leading to pulse width distortion and increased power dissipation, which is challenging to address with existing filtering solutions in RF applications.
Innovation Solution
A circuit and method that includes a driver circuit, a bias circuit with averaging and comparator components to balance rise and fall times, ensuring a 50% duty cycle in the digital output signal, using cascode transistors and inverters to adjust the timing and reduce second-order harmonics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If switching-mode amplifiers use fast transition (square wave) to reduce transistor power dissipation, then power efficiency is improved, but high frequency harmonics are generated that exceed out-of-band spurious emission limits
Solution Approach 1:
The patent applies preliminary action by pre-balancing the rise and fall times of the square wave signal before amplification. A bias circuit adjusts the duty cycle of the input signal to compensate for anticipated pulse width distortion in the amplifier stage, ensuring that the output signal maintains a balanced 50% duty cycle despite parasitic capacitance effects. This preemptive adjustment prevents excessive harmonic generation while maintaining the efficiency benefits of switching-mode operation.
2Device complexity
If parasitic capacitances are present in the amplifier stage, then device simplicity is maintained, but pulse width distortion occurs causing duty cycle deviation and even-order harmonics
Solution Approach 1:
The patent implements feedback by using a bias circuit that monitors the average voltage level of the amplifier output signal and uses this information to adjust the bias condition of the amplifier stage. The bias circuit compares the output signal average voltage with a reference and dynamically adjusts the gate bias voltage to compensate for pulse width distortion caused by parasitic capacitances. This feedback mechanism eliminates even-order harmonics without requiring complex circuit modifications.
3Object-generated harmful factors
If off-chip filters are used to reduce harmonics, then emission limits are met, but cost increases and power loss occurs
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitances into a beneficial mechanism by utilizing the inherent capacitance in the amplifier stage to create a natural pulse width modulation effect. By carefully controlling the bias conditions and rise/fall times, the circuit transforms what would normally be a source of distortion into a mechanism that shapes the output waveform to have reduced harmonic content, eliminating the need for external filters and their associated power losses.
Data Source
AI summary
A switching-mode power amplifier includes a driver circuit having an input for receiving a radio frequency (RF) signal, an output for outputting a digital output signal, and a bias port for receiving a bias signal, and a bias circuit having a first input coupled to the output of the driver circuit for receiving the digital output signal, a second input coupled to the input of the driver circuit for receiving the RF signal, and an output coupled to the bias port of the driver circuit for providing the bias signal to the driver circuit.