Switching Regulator 100 Percent Duty Cycle Control

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Solution Overview

Problem

Conventional switching regulators are limited to less than 100% duty cycle due to requirements from control circuitry, which restricts the minimum input voltage needed to support a regulated output, impacting their operational efficiency, especially in applications requiring higher charge currents or lower input voltages.

Innovation Solution

A switching regulator circuit that includes a ramp generator and comparator to produce a modulation signal, allowing the switching transistor to operate in a 100% duty cycle mode by turning on for full periods of the ramp signal when the error signal exceeds the ramp signal's maximum value, enabling seamless transitions between PWM and 100% DC modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional control circuitry with slope compensation is used, then the regulator operates reliably with proper reset every switching period, but the duty cycle is limited to less than 100%

Engineering Contradiction:
Improvecontrol circuitry reliabilityVSAvoidduty cycle range
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic switching between two control modes: PWM mode for normal operation and 100% duty cycle mode when the error signal exceeds the ramp signal maximum. This dynamic adaptation allows the system to overcome the fixed duty cycle limitation of conventional slope compensation while maintaining reliability in each operating mode.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operating parameters of the control circuitry by introducing a dual-mode system where the duty cycle parameter can dynamically transition from PWM-controlled values to 100% duty cycle. This parameter change enables the system to expand its adaptability without compromising the reliability of the control circuitry.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If maximum duty cycle is limited to less than 100%, then control circuitry can be reset every switching period, but the minimum input voltage must be higher

Engineering Contradiction:
Improvecontrol circuitry operationVSAvoidinput voltage requirement
Core Design Contradiction:
Ease of operationVSUse of energy by moving object

Solution Approach 1:

The system dynamically switches between PWM mode and 100% duty cycle mode based on the error signal magnitude. When the error signal exceeds the ramp signal maximum, the system transitions to 100% duty cycle mode, allowing operation at lower input voltages while maintaining ease of control circuitry operation through the seamless mode transition mechanism.

Inventive Principle:
Principle #15Dynamics

3Productivity

If PWM mode is used for regulation, then the switch operates with duty cycle control, but the charge current is limited

Engineering Contradiction:
Improveregulation efficiencyVSAvoidcharge current
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent enables continuous operation at 100% duty cycle when the error signal exceeds the ramp signal maximum, allowing the switching transistor to remain continuously on and deliver maximum charge current to the load. This continuous useful action eliminates the duty cycle limitation on charge current while maintaining regulation efficiency through the dual-mode control architecture.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentEP2973971B1Systems and methods for 100 percent duty cycle in switching regulators
Publication Date: 2018.05.23 QUALCOMM INC
  • EP2973971B1 patent drawingFigure 1
  • EP2973971B1 patent drawingFigure 2
  • EP2973971B1 patent drawingFigure 3

AI summary

The present disclosure includes systems and methods for 100% duty cycle in switching regulators. A switching regulator circuit includes a ramp generator to produce a ramp signal having a period and a comparator to receive the ramp signal and an error signal, and in accordance therewith, produce a modulation signal. In a first mode of operation, the ramp signal increases to intersect the error signal, and in accordance therewith, changes a state of a switching transistor during each period of the ramp signal. In a second mode of operation, the error signal increase above a maximum value of the ramp signal, and in accordance therewith, the switching transistor is turned on for one or more full periods of the ramp signal.