Switching Regulator Clock Timing for ZVS at Light Load
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional switching regulators face instability in light load efficiency due to the inability to achieve zero voltage switching (ZVS) while operating in constant frequency, which is problematic for load circuits requiring specific frequency ranges.
Innovation Solution
A switching regulator design that includes a power stage circuit, control circuit, and operation clock signal generator circuit, which generates a clock signal based on phase node voltage during a tolerance period to optimize turn-on time points, ensuring operation within a tolerable frequency range and improving light load efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the switching regulator operates in constant frequency mode, then the load circuit can operate within its required frequency range, but zero voltage switching cannot be achieved resulting in poor light load efficiency
Solution Approach 1:
The patent applies dynamics by making the switching frequency adjustable within a tolerable range rather than strictly constant. The control circuit dynamically selects switching timing within a tolerance period to achieve zero voltage switching while maintaining frequency stability within acceptable bounds, resolving the contradiction between constant frequency operation and energy efficiency.
Solution Approach 2:
The patent changes the frequency parameter from a fixed constant value to a variable within a tolerable range. By allowing frequency to vary within specified bounds and selecting optimal switching moments within a tolerance period, the system achieves both frequency stability for load circuits and improved light load efficiency through zero voltage switching.
2Loss of energy
If the turn-on time point is adjusted to achieve zero voltage switching, then light load efficiency is improved, but the operation frequency may go beyond the acceptable range
Solution Approach 1:
The system dynamically adjusts the switching timing within a constrained tolerance period rather than allowing unrestricted frequency variation. This dynamic adjustment within bounds enables zero voltage switching for improved efficiency while ensuring frequency remains within the acceptable range required by load circuits.
Solution Approach 2:
The control circuit preliminarily determines a tolerance period based on the required frequency range before actual switching occurs. Within this pre-established tolerance period, the system selects the optimal turn-on time point to achieve zero voltage switching, ensuring frequency stability is maintained while improving efficiency.
3Loss of energy
If the phase node voltage is monitored during ringing period, then available turn-on time points can be identified, but the control complexity increases
Solution Approach 1:
The control circuit uses feedback by monitoring the phase node voltage during the ringing period to identify available turn-on time points. This voltage feedback enables the system to detect when zero voltage switching conditions are met, allowing efficient operation while the feedback mechanism is implemented through standard control circuitry.
Solution Approach 2:
The phase node voltage serves as an intermediary signal that mediates between the power stage and control circuit. By using this existing voltage signal as feedback, the system can identify optimal switching moments without requiring additional complex sensing circuits, thus improving efficiency while limiting complexity growth.
Data Source
AI summary
A switching regulator includes: a power stage circuit, a control circuit and an operation clock signal generator circuit. The operation clock signal generator circuit includes: a time point option unit generating a time point option signal according to a phase node voltage during a ringing period subsequent to a blanking period, to indicate at least one available turn-on time point, or generating a lowest voltage time point signal according to the phase node voltage during a tolerance period, to indicate a lowest voltage time point; and a time point deciding unit deciding the tolerance period according to a base clock signal and a tolerable frequency range and select the available turn-on time point or the lowest voltage time point within the tolerance period as a decided time point, to generate the operation clock signal.