Semiconductor Chip Structure With Symmetric ID Paths for 3D Data Routing
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Solution Overview
Problem
The challenge of accurately transmitting data in three-dimensional stack structures of semiconductor chips remains unsolved, particularly in ensuring that data is correctly routed to each chip in a high-density and high-integration packaging scenario.
Innovation Solution
A semiconductor chip design featuring symmetrically distributed ID and data transmission paths perpendicular to the active surface, coupled with an ID decoding circuit to generate data selection signals, ensuring accurate data transmission to corresponding internal receiving circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional stack structure is adopted for high density and high integration packaging, then packaging density and integration are improved, but data transmission accuracy to each chip deteriorates
Solution Approach 1:
The patent divides the single ID transmission path into multiple symmetrically distributed ID transmission paths (first ID transmission path and second ID transmission path). Each path is independently configured to transmit ID signals, enabling segmented signal transmission that improves reliability while maintaining high-density packaging
Solution Approach 2:
Instead of using a single centralized ID transmission path, the patent inverts the approach by using multiple symmetrically distributed paths. The ID decoding circuit receives signals from multiple paths and decodes them to generate data selection signals, ensuring accurate data routing to each chip in the stack
2Measurement precision
If multiple ID transmission paths are symmetrically distributed, then data routing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent employs symmetrical distribution of ID transmission paths around a central axis, creating a balanced structure that simplifies routing logic. The first and second ID transmission paths are symmetrically positioned, allowing the ID decoding circuit to use consistent decoding logic for both paths, thereby managing complexity through symmetry rather than asymmetry
Solution Approach 2:
The ID decoding circuit is designed to universally decode ID signals from either the first or second ID transmission path using the same decoding logic. The circuit can selectively receive ID signals from different paths and generate corresponding data selection signals, providing multi-functional capability without increasing operational complexity
Data Source
AI summary
A semiconductor chip includes: a first ID transmission path, penetrating through a substrate of the semiconductor chip in a direction perpendicular to an active surface of the semiconductor chip; a second ID transmission channel, penetrating through the substrate in the direction perpendicular to the active surface of the semiconductor chip, and symmetrically distributed with the first ID transmission path based on a central axis of the semiconductor chip, where the central axis passes through a center of the semiconductor chip and is parallel to the active surface; and an ID decoding circuit, coupled to the first ID transmission path or the second ID transmission path, where the ID decoding circuit is configured to receive an ID signal and decode the ID signal to generate a data selection signal, where the semiconductor chip outputs data signals transmitted in a plurality of data transmission paths to corresponding internal receiving circuits respectively.