Symmetric Matrix Processing Element for AI Forward and Backpropagation

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Solution Overview

Problem

Current processing technologies, such as GPUs and FPGAs, face inefficiencies in performing complex matrix operations required for artificial intelligence tasks, particularly due to latency issues and limitations in handling both forward and backpropagation directions without reloading data, which hampers real-time computational performance.

Innovation Solution

A Symmetric Matrix Processing Element is designed to efficiently read, write, and process matrix data in parallel, enabling rapid forward and backpropagation calculations without reloading weight matrices, utilizing a wide SRAM for simultaneous access and operation of entire rows, and a control system to manage data flow through MAC units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional Von Neumann architecture is used for matrix operations, then flexibility in performing any calculation is maintained, but computational time becomes extremely long due to sequential processing iterations

Engineering Contradiction:
Improvecalculation flexibilityVSAvoidcomputational time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The processing element is segmented into specialized functional units including multiple MAC units arranged in a grid pattern, each capable of independent parallel operation. This segmentation allows simultaneous execution of multiple matrix operations that would otherwise require sequential processing, dramatically reducing computational time while maintaining calculation flexibility through configurable data flow paths.

Inventive Principle:
Principle #1Segmentation

2Productivity

If data is repeatedly loaded from memory for each processing iteration, then processing can be performed, but the time required becomes very long due to memory access latency

Engineering Contradiction:
Improveprocessing throughputVSAvoidmemory access time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Weight matrices are pre-loaded into local memory structures within the processing element before computation begins. The architecture includes on-chip memory buffers that hold weight data throughout the forward and backward propagation processes, eliminating the need for repeated memory accesses during processing iterations and significantly reducing memory access time.

Inventive Principle:
Principle #10Preliminary action

3Speed

If specialized processors like GPUs are used for matrix operations, then processing speed is improved, but it remains difficult to perform complex AI calculations efficiently due to data reloading requirements

Engineering Contradiction:
Improveprocessing speedVSAvoiddata reloading time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The processing element maintains continuous computation by keeping weight matrices resident in local memory throughout both forward propagation and backward propagation phases. Data flows continuously through the MAC units without interruption for reloading, enabling uninterrupted computational sequences that maximize processing speed while eliminating idle time associated with data reloading.

Inventive Principle:
Principle #20Continuity of useful action

4Ease of manufacture

If weight matrices are stored in standard memory configuration, then storage is simple, but efficient simultaneous access to entire rows for parallel processing is not achieved

Engineering Contradiction:
Improvememory organization simplicityVSAvoidparallel access efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The memory architecture implements a two-dimensional array organization for weight matrices, where weights are arranged in rows and columns corresponding to their mathematical indices. This dimensional organization allows simultaneous access to entire rows or columns through row-column addressing mechanisms, enabling parallel MAC units to efficiently retrieve multiple weight values in a single operation cycle without complicating the fundamental memory structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11983616B2Methods and apparatus for constructing digital circuits for performing matrix operations
Publication Date: 2024.05.14 EXPEDERA INC
  • US11983616B2 patent drawing
  • US11983616B2 patent drawing
  • US11983616B2 patent drawing

AI summary

Artificial intelligence is an increasingly important sector of the computer industry. However, artificial intelligence is very computationally intensive field. Fortunately, many of the required calculations can be performed in parallel such that specialized processors can greatly increase computation performance. In particular, Graphics Processor Units (GPUs) are often used in artificial intelligence. Although GPUs have helped, they are not ideal for artificial intelligence. Specifically, GPUs are used to compute matrix operations in one direction with a pipelined architecture. However, artificial intelligence is a field that uses both forward propagation computations and back propagation calculations. To efficiently perform artificial intelligence calculations, a symmetric matrix processing element is introduced. The symmetric matrix processing element can perform forward propagation and backward propagation calculations just as easily. Furthermore, both of these calculations can be performed without reloading weight matrix values.