Frequency Synthesizer Loop Bandwidth Switching for Low-Noise Locking
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Solution Overview
Problem
Current frequency synthesizers in Bluetooth systems face a trade-off between fast frequency locking for carrier frequency offset and drift tests, which requires a wide loop bandwidth, and maintaining low noise levels for modulation characteristics, which is compromised by increased noise entry with wider bandwidths.
Innovation Solution
A frequency synthesizer with an adjustable loop bandwidth that can switch between higher and lower bandwidths based on operational modes, allowing for optimal performance in carrier frequency offset and drift tests while minimizing noise interference during transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency synthesizer is designed with a wide loop bandwidth, then the frequency locking speed is faster and frequency drift is smaller, but noise from other circuit areas enters the frequency synthesizer more easily, resulting in worse error vector magnitude (EVM) performance
Solution Approach 1:
The patent implements dynamic loop bandwidth adjustment by switching between a first loop bandwidth (higher) during frequency acquisition and a second loop bandwidth (lower) during stable operation. This dynamic adaptation allows the system to achieve fast frequency locking when needed while minimizing noise interference during normal transmission, thereby resolving the contradiction between locking speed and noise performance.
Solution Approach 2:
The patent changes the loop bandwidth parameter based on operational phase: using a higher first loop bandwidth for rapid frequency acquisition and carrier offset correction, then switching to a lower second loop bandwidth for maintaining frequency stability with reduced noise susceptibility. This parameter adjustment strategy enables the system to optimize both frequency locking speed and EVM performance at different operational stages.
2Device complexity
If the frequency synthesizer uses a single loop bandwidth design, then the structure is simple, but it cannot simultaneously achieve good performance in both carrier frequency offset and drift tests and modulation characteristics
Solution Approach 1:
The patent introduces dynamic loop bandwidth switching capability while maintaining relatively simple circuit architecture. By using a control circuit to switch between two loop bandwidth configurations based on operational mode, the system achieves adaptability for different performance requirements without significantly increasing structural complexity, thus resolving the contradiction between simplicity and versatility.
Data Source
AI summary
The present invention provides a transceiver circuit including a transmitter circuit, a frequency synthesizer and control circuit. The transmitter circuit is configured to generate a transmission signal, wherein the transmission signal is transmitted through an antenna. The frequency synthesizer is configured to generate a clock signal for the transmitter circuit to generate the transmission signal. The control circuit is configured to generate a first control signal to control the frequency synthesizer to determine a loop bandwidth of the frequency synthesizer; wherein when the transceiver circuit operates in a standby mode, the control circuit generates the first control signal to make the frequency synthesizer have a first loop bandwidth; and after a period of time after the transceiver circuit is switched from the standby mode to a transmission mode, the control circuit generates the first control signal to make the frequency synthesizer have a second loop bandwidth.