Frequency Synthesizer Unlock Detection Using Rotation Vector Monitoring

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Solution Overview

Problem

Existing frequency synthesizers using PLL control face challenges in quickly detecting an unlock state due to delayed determination caused by intermittent arithmetic operations and clock-dependent detection methods, which do not adequately satisfy the need for instant unlock detection.

Innovation Solution

A frequency synthesizer that monitors the control voltage or signal levels for deviations from a set range, using a monitoring means to output an unlock detection signal, and includes a frequency pull-in mechanism to add a voltage for gain control, enabling instant detection of the PLL unlock state by continuously monitoring the control voltage or signal levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the frequency synthesizer uses intermittent arithmetic operations and clock-dependent detection to monitor the scalar quantity of the vector, then the device complexity is reduced, but the detection speed becomes slow and delayed by the amount of time for digital signal arithmetic operation

Engineering Contradiction:
Improvedetection speedVSAvoiddetection mechanism complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent extracts the essential detection parameter (scalar quantity of the vector) from the complex digital signal processing chain and monitors it directly. By taking out this key parameter and monitoring it continuously, the system achieves fast detection without being burdened by the complexity of intermittent arithmetic operations on the entire digital signal.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a monitoring mechanism that acts as an intermediary between the vector processing unit and the control system. This intermediary continuously monitors the scalar quantity and generates unlock detection signals immediately when thresholds are exceeded, bridging the gap between complex signal processing and simple detection requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the frequency synthesizer performs arithmetic operations and vector multiplication steps intermittently by a clock, then the use of energy is reduced, but the determination is delayed resulting in inability to satisfy the request for instantly detecting the unlock state

Engineering Contradiction:
Improveunlock state detection reliabilityVSAvoiddetection delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements continuous monitoring of the scalar quantity of the vector, replacing intermittent clock-dependent detection. This continuous action ensures that the unlock state is detected immediately when it occurs, eliminating detection delays while maintaining energy efficiency by monitoring only the essential parameter rather than performing full arithmetic operations continuously.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The patent performs preliminary calculation of the scalar quantity of the vector during the normal signal processing flow, so that when the vector is already computed, its scalar quantity is readily available for immediate monitoring. This preliminary action prepares the detection data in advance, enabling instant unlock detection without additional computational delay.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8466717B2Frequency synthesizer
Publication Date: 2013.06.18 NIHON DEMPA KOGYO CO LTD
  • US8466717B2 patent drawing
  • US8466717B2 patent drawing
  • US8466717B2 patent drawing

AI summary

The provision of a technique capable of determining a state where PLL control does not operate normally instantly or in advance in a frequency synthesizer that frequency-divides, A/D converts, and quadranture-detects a frequency signal from a voltage controlled oscillating unit, and extracts a rotation vector rotating at a frequency difference between the frequency signal used for the detection and the A/D converted frequency signal, and integrates a difference between a frequency of the above rotation vector and a set frequency to set an integration result as a control voltage to the voltage controlled oscillating unit. The control voltage to be input to the voltage controlled oscillating unit is monitored, and it is determined whether or not a level of the monitored control voltage deviates from a set range determined in advance, and an unlock detection signal is output. In a structure in which the rotation vector is multiplied by a reverse rotation vector reversely rotating at a frequency determined in rough increments according to the set frequency to reduce a velocity of the rotation vector, a determination result whether or not a length of the rotation vector whose velocity is reduced (a scalar quantity) or a correction signal for gain control deviates from a range set in advance is further considered.