Systolic Array Column Validation for CNN Efficiency
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Solution Overview
Problem
Systolic arrays face inefficiencies in processing large-scale convolutional neural network calculations due to suboptimal utilization of processing elements and inefficient handling of padding values, leading to reduced performance and increased power consumption.
Innovation Solution
A systolic array architecture is designed with configurable processing elements arranged in rows and columns, enabling horizontal and vertical data shifting, and using column validation bits to disable inactive columns and avoid padding by cyclically rotating data, thereby improving processing efficiency and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If systolic arrays use traditional padding methods to handle boundary conditions in CNN calculations, then completeness of convolution operation is improved, but processing efficiency deteriorates and power consumption increases
Solution Approach 1:
The patent extracts and removes the padding operation from the systolic array processing pipeline entirely. By using column validation bits to identify and exclude boundary columns that would require padding, the system processes only valid data columns, eliminating the need for padding operations and their associated performance penalties and power consumption.
Solution Approach 2:
The patent introduces dynamic column validation bits that can be configured to enable or disable specific columns based on the current processing stage and data validity. This dynamic control allows the systolic array to adaptively process only valid data columns, avoiding static padding operations and improving overall processing efficiency.
2Quantity of substance
If systolic arrays process all columns including boundary columns requiring padding, then full data coverage is improved, but resource utilization deteriorates
Solution Approach 1:
The patent applies local quality by differentiating between valid and invalid columns through validation bits. Each column can be independently marked as valid or invalid, allowing the systolic array to process only the necessary subset of columns with appropriate quality control, rather than uniformly processing all columns including those requiring padding.
Solution Approach 2:
The patent uses partial action by processing only the valid portion of columns identified by validation bits, rather than processing all columns. This selective processing approach avoids the excessive action of including boundary columns that would require padding, thereby improving resource utilization while maintaining complete coverage of valid data.
3Reliability
If systolic arrays include padding operations for boundary handling, then correctness of output is improved, but power consumption increases
Solution Approach 1:
The patent converts the potential harm of incomplete boundary processing into a benefit by using column validation bits to systematically identify and exclude invalid columns. This approach ensures correctness of output through validation-based filtering while avoiding the power consumption associated with padding operations, effectively turning a potential problem into a solution.
Data Source
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AI summary
A system and method for performing computational processing by a systolic array. The systolic array including an array of processing elements (PEs) arranged in rows and columns; logic to perform a horizontal shift operation, wherein the horizontal shift operation is performed across the entire systolic array; and logic to mark columns of PEs as enabled or disabled, wherein the systolic array is horizontally divided into horizontal groups, and wherein when performing the horizontal shift operation, valid data that crosses from a first column of PEs of a first horizontal group to a second column of PEs of a second horizontal group is invalidated, wherein the first horizontal group is adjacent to the second horizontal group.