Systolic Array Feature Operation Timing for Lower Data Delay
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Solution Overview
Problem
The data operation process of systolic arrays in AI processors causes significant delays, affecting the efficiency of these arrays.
Innovation Solution
A data processing apparatus and method that controls the clock cycle of data pulsation in systolic arrays by implementing a feature operation module with n groups of feature operation units, where each group is connected according to association and feature operation logic, and the start time of adjacent groups is staggered by at least one preset clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If data operation process is implemented in systolic array, then computing power is achieved, but data operation delay increases
Solution Approach 1:
The patent applies preliminary action by pre-aligning the clock cycles of feature operation units before data operations begin. The clock cycle alignment mechanism ensures that all feature operation units are synchronized and ready to process data simultaneously, preventing delays during the actual computation phase. This pre-synchronization approach eliminates waiting time during data flow through the systolic array.
Solution Approach 2:
The patent implements periodic action through the clock cycle alignment mechanism that rhythmically synchronizes the operation of multiple feature operation units. By using periodic clock signals with aligned phases, the system ensures that data flows smoothly through the systolic array without timing mismatches, maintaining continuous operation and reducing idle delays between computational stages.
2Measurement precision
If feature operation units are connected according to association operation logic, then operation precision is maintained, but system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the feature operation process into multiple independent feature operation units, each handling specific portions of the computation. These units are connected through a standardized clock cycle alignment interface, which simplifies the overall system architecture while maintaining precise operational control. The segmentation allows each unit to operate independently with clear, manageable connections rather than complex interdependencies.
Solution Approach 2:
The patent uses parameter changes by adjusting and aligning the clock cycle parameters of different feature operation units. By modifying the timing parameters (clock phases and frequencies) to be synchronized, the system achieves precise coordination between units without requiring complex control logic. This parameter-based synchronization simplifies the connection architecture while ensuring operational precision.
Data Source
AI summary
A data processing apparatus is provided with a systolic array configured to perform a feature operation on feature data obtained from feature extraction on service data of a target service. The feature data includes n pieces of feature subdata arranged in sequence. The systolic array includes a feature operation module including n groups of feature operation units configured to perform the feature operation on the n pieces of feature subdata. The n groups of feature operation units are connected according to association operation logic between the n pieces of feature subdata. A group of feature operation units includes a first operation subunit and a second operation subunit that are connected according to feature operation logic of a corresponding feature subdata. The n groups of feature operation units perform the feature operation on the n pieces of feature subdata in a preset sequence corresponding to the association operation logic.