Systolic Memory Circuit Layout With Delayed Read Data Registers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The organization and wiring of RAMs to deliver delayed data to the stages of systolic array circuits in configurable integrated circuits impact placement, area, and the number of RAM primitives, which is inefficient for AI inference computations.
Innovation Solution
A systolic array circuit design that includes first registers coupled in series, memory circuits coupled to the first registers, downstream circuits coupled in series, and second registers between the memory circuits and downstream circuits, optimizing the use of memory circuits by delaying subsets of read data bits to improve resource efficiency and timing characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If RAMs are organized and wired to deliver delayed data to systolic array circuits, then data delivery timing is improved, but placement complexity and area increase
Solution Approach 1:
The patent segments the data delivery path by introducing intermediate storage circuits between the RAMs and the systolic array circuits. These intermediate circuits divide the data delivery function into multiple stages, with each stage handling specific data subsets with specific timing requirements, thereby reducing overall placement complexity while achieving precise delay control.
Solution Approach 2:
The patent introduces intermediate storage circuits as mediators between the RAMs and the systolic array circuits. These intermediary circuits buffer and delay data subsets, allowing the system to achieve precise timing control without directly complex wiring between RAMs and all array stages, thus reducing placement complexity.
2Loss of time
If RAMs are organized and wired to deliver delayed data to systolic array circuits, then data delivery timing is improved, but the number of RAM primitives increases
Solution Approach 1:
The patent makes the intermediate storage circuits multi-functional by having them serve both as data buffers and as timing control elements. These circuits not only store data subsets but also control the timing of data delivery to different stages of the systolic array, eliminating the need for separate dedicated delay circuits and reducing the overall number of RAM primitives required.
Solution Approach 2:
The patent merges the data storage function and the timing delay function into a single intermediate storage circuit structure. By combining these functions, the system achieves the required data delivery delays without needing separate dedicated delay elements, thereby reducing the total number of RAM primitives needed.
3Productivity
If intermediate storage circuits are added between memory circuits and downstream circuits, then resource efficiency is improved, but device complexity increases
Solution Approach 1:
The patent introduces dynamic control signals that selectively enable or disable different data delivery paths through the intermediate storage circuits. This dynamic control allows the same circuit structure to efficiently handle different computation patterns and data timing requirements, improving resource efficiency while keeping the physical circuit structure relatively simple and manageable.
Data Source
AI summary
A systolic array circuit includes memory circuits, storage circuits, and processing elements. Each of the memory circuits accesses first read data and second read data in response to a read address. The systolic array circuit is coupled to provide the first read data accessed from each of the memory circuits to a first one or more of the processing elements. The systolic array circuit is coupled to provide the second read data accessed from each of the memory circuits through one of the storage circuits to a second one or more of the processing elements.