T-Shaped Gate Selection Transistor for Flash Memory Density
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Solution Overview
Problem
The challenge in forming a gate for string selection transistors or ground selection transistors in flash memory devices is exacerbated by the thin floating gate, which complicates the formation of a gate with a T-shaped cross section and affects the density and scalability of information storage.
Innovation Solution
A selection transistor is fabricated with a gate electrode having recessed sidewall portions, a tunnel insulating layer, and a charge storage layer, where the gate electrode is formed with a T-shaped cross section, and source/drain regions are created on either side, enabling efficient data storage and retrieval in nonvolatile memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the floating gate is reduced in thickness to achieve high density and large-scale information storage, then storage density is improved, but the formation of a T-shaped gate cross section becomes difficult
Solution Approach 1:
The gate electrode is divided into multiple segments: a lower gate electrode portion and an upper gate electrode portion, separated by a first insulating layer. This segmentation allows the gate to be formed in a planar configuration rather than requiring a T-shaped cross section, making manufacturing feasible with thin floating gates while maintaining high storage density
Solution Approach 2:
The gate structure employs a nested configuration where the lower gate electrode portion is positioned beneath the upper gate electrode portion, with the first insulating layer separating them. This nested arrangement enables the gate to function effectively without requiring a complex T-shaped geometry, thus facilitating manufacturing while achieving high density storage
Data Source
AI summary
Provided are a selection transistor and a method of fabricating the same. A selection transistor can be formed on an active region in a semiconductor substrate to include a gate electrode that includes recessed portions of a sidewall of the gate electrode which are recessed inward adjacent lower portions of the gate electrode to define a T-shaped cross section of the gate electrode. A tunnel insulating layer can be located between the gate electrode and the active region.


