TAB Package Pad Arrangement for LCD IC Chip Size Reduction
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Solution Overview
Problem
Conventional LCD modules with TAB packages face challenges in arranging output pads along the upper longer side of the IC chip without increasing the size of the package, as they typically require a wider peripheral region, leading to higher production costs and larger product sizes.
Innovation Solution
The proposed solution involves arranging first and second output pads along the longer sides of the IC chip, with the second output pads located at offset positions, and forming corresponding output patterns on the base film to connect these pads without extending through the narrower peripheral region, allowing for a more compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If output pads are arranged along the upper longer side of the IC chip, then the number of output pads increases, but the peripheral region width must increase leading to larger package size
Solution Approach 1:
The patent applies dimensionality change by routing circuit patterns through the narrower peripheral region using a multi-layer base film structure. Output patterns are formed on different layers (first and second peripheral regions) and connected through intermediate patterns, effectively utilizing the vertical dimension (layer stacking) to accommodate more output pads without increasing the horizontal package footprint.
Solution Approach 2:
The base film is divided into multiple layers with distinct peripheral regions (first and second peripheral regions). This segmentation allows output patterns to be distributed across different layers and regions, enabling the routing of numerous output signals through the narrower peripheral area without congestion, thus increasing output pad capacity while maintaining compact package dimensions.
2Quantity of substance
If the peripheral region width increases to accommodate more output pads, then the number of output pads increases, but production cost increases
Solution Approach 1:
By utilizing the vertical dimension through multi-layer base film construction, the patent enables high-density output pad arrangement within the existing peripheral width constraints. This eliminates the need for costly wider peripheral regions while accommodating the required number of output pads, thereby reducing production costs associated with larger material usage and manufacturing complexity.
3Length of stationary object
If input patterns pass through the narrower second peripheral region, then the package size is reduced, but the number of accommodated patterns is limited
Solution Approach 1:
The base film is segmented into multiple layers with dedicated peripheral regions for different signal types. Input patterns are routed through specific layers and regions, while output patterns use other layers and regions. This segmentation allows the narrower peripheral region to accommodate complex multi-layer routing without increasing package size, as each layer provides independent routing capacity.
Solution Approach 2:
The patent resolves the complexity issue by transitioning to three-dimensional multi-layer routing. Instead of congesting two-dimensional space, circuit patterns are distributed across multiple vertical layers, allowing the narrower peripheral region to handle complex signal routing capacity equivalent to or greater than wider single-layer designs.
Data Source
AI summary
Output pads on an integrated circuit (IC) chip are arranged along a first longer side and are arranged along a second longer side with input pads. The output pads are connected to respective output patterns formed on top and bottom surfaces of a base film. All the output patterns may pass over the first longer side. Alternatively, the output patterns connected to the output pads at the second longer side may pass over a shorter side. These pattern structures establish an effective pad arrangement without increasing the size of a TAB package, yet allowing reduced the chip size.