Test Access Port Driving Circuit Internal Control

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Solution Overview

Problem

The JTAG standard for testing integrated circuits allows access to the Test Access Port only through external terminals, limiting the flexibility and efficiency of the testing process.

Innovation Solution

A driving circuit that enables access to the Test Access Port from within the integrated circuit, allowing a microprocessor to control the test access, reducing test time and enabling read/write operations without external terminals, and allowing additional functions through a defined protocol.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If access to Test Access Port is limited to external terminals only, then the testing process requires physical access to integrated circuit, but the test time increases and flexibility decreases

Engineering Contradiction:
Improveaccess to Test Access PortVSAvoidtest time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent introduces a driving circuit as an intermediary component that mediates between the microprocessor and the Test Access Port. This driving circuit receives control signals from the microprocessor and generates the appropriate test signals (TDI, TMS, TCK, TDO) to control the TAP, enabling internal access without requiring external terminal connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The integrated circuit performs self-testing by using its own microprocessor to control the Test Access Port through the driving circuit. The system serves itself by generating test signals internally without requiring external testing equipment or physical access to external terminals, thereby reducing test time and increasing flexibility.

Inventive Principle:
Principle #25Self-service

2Adaptability or versatility

If external terminals are required for Test Access Port operations, then the testing process is standardized, but the versatility and additional functions are limited

Engineering Contradiction:
Improvetesting flexibilityVSAvoidterminal requirements
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The driving circuit is designed to perform multiple functions: it controls the Test Access Port for testing operations, enables communication between the microprocessor and TAP, and allows the integrated circuit to perform both self-testing and external testing modes. This multi-functionality increases versatility without significantly increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If read/write operations require external terminals, then the Test Access Port follows standard protocol, but the ability to perform operations during normal operation is lost

Engineering Contradiction:
Improveoperation efficiencyVSAvoidread/write capability
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The driving circuit enables continuous read/write operations to the Test Access Port registers without requiring external terminal connections. The microprocessor can perform testing operations during normal circuit operation or when external terminals are unavailable, maintaining continuous productivity and eliminating interruptions in the testing process.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS8892387B2Driving circuit of a test access port
Publication Date: 2014.11.18 STMICROELECTRONICS SRL
  • US8892387B2 patent drawing
  • US8892387B2 patent drawing
  • US8892387B2 patent drawing

AI summary

A driving circuit of a test access port is disclosed. The driving circuit includes an input terminal for receiving a first test data signal when the driving circuit is operating in an external test mode. The driving circuit is configured to receive a second test data signal (BS) carrying a test command to be executed on the test access port when the driving circuit is operating in an internal test mode. The driving circuit comprises a control logic circuit configured for processing the test command and generating therefrom an internal test data signal carrying the processed test command when the driving circuit is operating in the internal test mode. The driving circuit includes a selector configured for generating a selected test data signal, the selected test data signal being selected from the first test data signal when the driving circuit is operating in the external test mode.