TAP Router Circuit for At-Speed Scan Operations Without Dead States
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Solution Overview
Problem
The IEEE 1149.1 Test Access Port (TAP) struggles to effectively control at-speed Update & Capture and Shift & Capture operations due to dead states in its state machine transitions, limiting its ability to perform efficient scan operations in embedded IC circuits.
Innovation Solution
The TAP is augmented with additional circuitry, including a Command (CMD) circuit and a Dual Port Router, which allows for time division multiplexing of CMD signals onto the TMS input or detection of Exit1DR and PauseDR states to produce at-speed Update and Capture signals, enabling direct control of data registers and eliminating dead states during scan operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the TAP uses standard state machine transitions for Update & Capture and Shift & Capture operations, then the basic test functionality is maintained, but dead states occur that limit at-speed operation efficiency
Solution Approach 1:
The patent segments the TAP control functionality by introducing a separate CMD circuit that operates independently from the traditional TSM state machine. This allows the CMD circuit to handle Update and Capture operations without being constrained by the sequential state transitions of the TSM, thereby eliminating dead states and enabling at-speed operations.
Solution Approach 2:
The patent introduces a CMD circuit as an intermediary between the TMS input and the data register control logic. This CMD circuit receives multiplexed commands from TMS and directly generates Update and Capture signals, bypassing the inefficient TSM state transitions and enabling direct at-speed control of data registers.
2Productivity
If the TAP is augmented with additional circuitry for at-speed operations, then scan operation efficiency improves, but device complexity increases
Solution Approach 1:
The CMD circuit is designed to handle multiple operations (Update, Capture, and at-speed variants) through a unified interface that multiplexes commands from the existing TMS input. This multi-functional approach allows the additional circuitry to provide enhanced capabilities while reusing existing TAP infrastructure, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the CMD circuit with the existing TAP structure by multiplexing CMD signals onto the TMS input line. This integration approach combines the new at-speed functionality with the traditional TAP architecture, allowing both standard and enhanced operations to coexist within a unified circuit structure.
3Adaptability or versatility
If the TAP maintains its original state machine structure, then ease of operation is preserved, but adaptability to at-speed operations is limited
Solution Approach 1:
The CMD circuit automatically detects and responds to multiplexed commands from TMS, generating the appropriate Update and Capture signals without requiring manual intervention or complex external control logic. This self-service capability maintains ease of operation while enabling adaptability to at-speed requirements.
Solution Approach 2:
The CMD circuit operates by periodically sampling the TMS input line for multiplexed commands and generating corresponding control signals at the appropriate clock edges. This periodic operation mode maintains compatibility with standard TAP timing while providing adaptability for at-speed operations through command multiplexing.
Data Source
AI summary
In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.