TAP Scan Control for At-Speed Capture and Update
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Solution Overview
Problem
The IEEE 1149.1 Test Access Port (TAP) struggles to effectively control at-speed Update & Capture and Shift & Capture operations due to dead states in its state machine transitions, limiting its ability to perform efficient scan operations in embedded IC circuits.
Innovation Solution
The TAP is augmented with additional circuitry, including a Command (CMD) circuit and a Dual Port Router, which allows for time division multiplexing of CMD signals onto the TMS input or detection of Exit1DR and PauseDR states to produce at-speed Update and Capture signals, enabling direct control of data registers and eliminating dead states during scan operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the TAP uses traditional state machine transitions (UpdateDR → CaptureDR → ShiftDR), then the operations can be performed sequentially, but dead states are introduced between transitions, reducing operating speed
Solution Approach 1:
The patent maintains the TAP in a continuous ShiftDR state without transitioning to dead states. The CMD circuit receives commands during the ShiftDR state and performs Capture and Update operations continuously without interrupting the shift operation, eliminating idle time between operations.
Solution Approach 2:
The CMD circuit is pre-configured to receive and process commands during the ShiftDR state. By preparing Capture and Update signals in advance during the shift operation, the circuit eliminates the need to transition to separate states for these operations, maintaining continuous operation.
2Productivity
If the TAP transitions through multiple states (Exit1DR, PauseDR) to perform Capture and Update operations, then operational completeness is achieved, but the number of state transitions increases, reducing efficiency
Solution Approach 1:
The patent extracts the Capture and Update control functions from the traditional TAP state machine and implements them in a separate CMD circuit. This allows the main TAP to remain in a simple ShiftDR state while the CMD circuit handles complex control operations independently.
Solution Approach 2:
The CMD circuit acts as an intermediary between the TAP and the data register. It receives TCK and TMS signals, generates appropriate Capture and Update control signals, and interfaces with the data register, thereby simplifying the TAP state machine while maintaining full operational capability.
3Speed
If the TAP maintains continuous ShiftDR state for at-speed operations, then operating speed is improved, but the ability to perform traditional sequential operations is compromised
Solution Approach 1:
The CMD circuit is designed to handle multiple operation types (Capture, Update, and combinations) within a single ShiftDR state. By making the CMD circuit universal in its ability to perform different operations based on received commands, the system maintains both high speed and operational versatility.
Solution Approach 2:
The system dynamically adjusts its operation mode based on incoming CMD signals. While maintaining a continuous ShiftDR state for speed, the CMD circuit can dynamically initiate Capture or Update operations as needed, allowing the system to adapt between different operational requirements without state transitions.
Data Source
AI summary
In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.