Tape Carrier Wiring Pattern Width Variation for COF Reliability
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Solution Overview
Problem
COF semiconductor apparatuses face challenges in achieving finer wiring pitches and thinner films while maintaining mechanical strength and bond strength, leading to defects such as wiring patterns coming into contact with adjacent bump electrodes and disconnection or peeling off, especially at pitches smaller than 35 μm.
Innovation Solution
A tape carrier design with a wiring pattern that has a connecting section smaller in width than the remaining overlap part, ensuring the wiring pattern does not contact adjacent bump electrodes and improving mechanical and bond strength by maintaining a wider width in the remaining part of the overlap section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the wiring pattern width is reduced to achieve finer wiring pitch, then the wiring pitch can be made smaller (35 μm or less), but the mechanical strength and bond strength of the wiring pattern deteriorate, causing disconnection or peeling off
Solution Approach 1:
The wiring pattern is designed with different widths in different sections: a first section with width W1 that overlaps the semiconductor device has a larger width to ensure mechanical strength and bond strength, while a second section with width W2 that does not overlap has a smaller width to achieve finer wiring pitch. This local differentiation allows the wiring pattern to simultaneously achieve fine pitch and maintain sufficient strength where needed.
2Reliability
If the wiring pattern width is reduced to prevent contact with adjacent bump electrodes, then the reliability improves, but the mechanical strength and bond strength deteriorate
Solution Approach 1:
The wiring pattern width is locally optimized: in the first section overlapping the semiconductor device, the width W1 is larger to provide mechanical strength and bond strength, while in the second section not overlapping, the width W2 is smaller to prevent contact with adjacent bump electrodes. This spatial differentiation of width allows simultaneous achievement of reliability and strength.
3Length of stationary object
If the insulating tape and wiring pattern are made thinner to reduce overall thickness, then the COF semiconductor apparatus becomes thinner, but the mechanical strength and folding capability are compromised
Solution Approach 1:
The design maintains overall thinness of the COF semiconductor apparatus while locally reinforcing the wiring pattern in the first section (width W1) that overlaps the semiconductor device. This localized width increase provides necessary mechanical strength and bond strength without significantly increasing the overall thickness of the apparatus.
Data Source
AI summary
A tape carrier of the present invention includes an insulating tape and a wiring pattern formed on the insulating tape. The wiring pattern includes a connecting section via which the wiring pattern is connected to a bump electrode. The connecting section is provided at a part of an overlap part of the wiring pattern, which overlap part overlaps a semiconductor device when the semiconductor device is mounted on the wiring pattern. The connecting section of the wiring pattern is smaller in wiring width than the remaining part of the overlap part, which remaining part is other than the connecting section.