Tapered Active Pattern Reduces Parasitic Capacitance in Oxide TFTs
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Solution Overview
Problem
Thin film transistors using semiconductive oxides face issues with excessive lateral protrusion of the semiconductive oxide pattern, leading to parasitic capacitance and degradation of image quality, particularly in large-sized display devices, due to the difficulty in forming uniform polycrystalline silicon layers and the high manufacturing costs associated with them.
Innovation Solution
A thin film transistor design featuring a semiconductive oxide active pattern with sidewall taper angles greater than the source metal pattern, which underlaps the source metal pattern and minimizes lateral protrusion, using a process that includes forming a semiconductive oxide layer, a source metal layer, and etching with a photoresist pattern and etchant that prevents excessive capacitance without requiring additional masks or fluorine-containing compounds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a photoresist pattern with thickness gradient is used for half-tone exposure to form semiconductive oxide pattern, then the semiconductive oxide pattern can be formed, but the pattern protrudes excessively beyond the source metal pattern end, creating excessive parasitic capacitance
Solution Approach 1:
The patent applies asymmetry by creating different taper angles for the active pattern and source metal pattern. The active pattern has a first taper angle that is greater than the second taper angle of the source metal pattern, resulting in an underlapped configuration where the active pattern does not excessively protrude beyond the source metal pattern end, thereby reducing parasitic capacitance while maintaining proper pattern formation
Solution Approach 2:
The patent changes the geometric parameters by specifying that the first taper angle of the active pattern is greater than the second taper angle of the source metal pattern. This parameter change transforms the conventional overlapped configuration into an underlapped configuration, controlling the lateral extension of the semiconductive oxide pattern to minimize parasitic capacitance
2Reliability
If polycrystalline silicon is used to achieve high electron mobility, then driving characteristics improve, but crystallization process is required at each location, making uniform formation on large substrates difficult and increasing manufacturing cost
Solution Approach 1:
The patent replaces expensive polycrystalline silicon with semiconductive oxide, which can be formed through low-temperature processes without requiring complex crystallization steps. This substitution maintains adequate electron mobility while significantly simplifying the manufacturing process and reducing costs, especially for large-sized substrates
Solution Approach 2:
The patent changes the material parameter from polycrystalline silicon to semiconductive oxide, which fundamentally alters the formation process. Semiconductive oxide can be deposited at lower temperatures and does not require location-by-location crystallization, enabling uniform formation across large substrates and reducing manufacturing complexity
Data Source
AI summary
A thin film transistor includes a gate electrode, an active pattern overlapping with the gate electrode and including a semiconductive oxide, and a source metal pattern disposed on the active pattern and including a source electrode and a drain electrode spaced apart from the source electrode. The active pattern underlaps an entire portion of a lower surface of the source metal pattern and minimally protrudes beyond lateral ends of the source metal pattern due to the active pattern having sidewall taper angles that are substantially greater than corresponding and adjacent sidewall taper angles of the overlying source metal pattern. Thus parasitic capacitance may be reduced and performance enhanced.