Tapered Connection Bump for Semiconductor Package Stability
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Solution Overview
Problem
Semiconductor packages face challenges in achieving high performance, large capacity, miniaturization, and lightweight design, particularly in maintaining contact stability of bumps and pads, which is crucial for advanced electronic devices.
Innovation Solution
A semiconductor package design featuring a first chip substrate with a through via and an upper passivation layer having a trench, an upper pad extending along the trench, and a connection bump that increases in width as it moves away from the substrate, electrically connecting with a lower pad on a second chip substrate, enhancing bonding force and contact stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the connection bump width is increased to improve bonding force and contact stability, then the reliability of the semiconductor package is improved, but the device size increases
Solution Approach 1:
The connection bump is designed with an asymmetric tapered shape where the width increases from the first chip substrate toward the second chip substrate. This asymmetric geometry provides a larger bonding area at the interface with the second chip substrate for improved contact stability, while maintaining a smaller footprint at the first chip substrate to minimize overall device size.
Solution Approach 2:
The connection bump utilizes the vertical dimension by increasing in width as it extends from the first chip substrate to the second chip substrate. This dimensional transition allows the bump to achieve adequate bonding area without increasing the planar footprint, effectively resolving the contradiction between contact stability and device size.
2Weight of moving object
If miniaturization is pursued to reduce device size, then the weight and volume are reduced, but the contact stability of bumps and pads deteriorates
Solution Approach 1:
The tapered asymmetric shape of the connection bump allows miniaturization of the package footprint while compensating for reduced contact area through increased width at the bonding interface with the second chip substrate, thereby maintaining contact stability despite overall size reduction.
Solution Approach 2:
The connection bump geometry is optimized by changing the width parameter along its height, creating a tapered structure that maintains adequate bonding dimensions at critical interfaces while allowing the overall package to be miniaturized.
Data Source
AI summary
Provided is a semiconductor package including a first chip substrate including a first surface and a second surface, a through via passing through the first chip substrate, an upper passivation layer including a trench on the second surface of the first chip substrate, the trench exposing at least a portion of the second surface of the first chip substrate, an upper pad electrically connected with the through via on the trench, a second chip substrate including a third surface and a fourth surface, a lower pad electrically connected to the second chip substrate on the third surface of the second chip substrate, and a connection bump electrically connecting the upper pad with the lower pad and contacting the lower pad, wherein a width of the connection bump increases as the connection bump becomes farther away from the first surface of the first chip substrate.