Tapered Source/Drain Contact Profile for Lower FinFET RC Delay
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Solution Overview
Problem
As semiconductor devices continue to scale down, parasitic resistance and capacitance associated with conductive contacts/vias in FinFET and GAA devices increase, leading to larger RC time constants and slower transistor speeds.
Innovation Solution
Optimizing the profile of conductive contacts/vias by forming a large spacer layer to reduce capacitance and enlarging the contact silicide area to decrease parasitic resistance, while configuring a tapered cross-sectional side view profile to enhance electrical isolation and prevent shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of transistor components is reduced to increase functional density, then production efficiency is improved and costs are lowered, but parasitic resistance and capacitance increase leading to larger RC time constants
Solution Approach 1:
The patent applies local quality by creating a non-uniform contact profile with varying dimensions at different locations. The contact has a larger top surface area compared to its cross-sectional area, concentrating the beneficial effect of reduced parasitic resistance at the contact interface where it is most needed, while maintaining smaller overall dimensions for high functional density.
Solution Approach 2:
The patent transitions from a conventional uniform cylindrical contact to a multi-dimensional contact structure with different surface areas at various levels. By creating a contact with enlarged top surface area relative to its cross-section, the invention exploits dimensional variation to simultaneously achieve low parasitic resistance (requiring large area) and high functional density (requiring small footprint).
2Quantity of substance
If the contact cross-sectional area is reduced to increase functional density, then more contacts can be packed per chip area, but parasitic resistance increases
Solution Approach 1:
The contact structure implements local quality by having different cross-sectional areas at different heights. The top surface area is enlarged to reduce parasitic resistance, while the cross-sectional area at the base remains small to allow high contact density. This spatial variation in geometry allows the contact to satisfy contradictory requirements at different locations.
3Productivity
If the contact dimensions are reduced to increase functional density, then chip area utilization improves, but fabrication precision requirements increase due to smaller features
Solution Approach 1:
The contact structure performs preliminary action by establishing a multi-level geometry that inherently provides manufacturing tolerance. The enlarged top surface area creates a larger target for subsequent fabrication steps, making the process less sensitive to precision errors while maintaining small overall dimensions for high density.
Data Source
AI summary
A semiconductor device includes an active region that extends in a first horizontal direction. A source/drain component is disposed over the active region. A source/drain contact is disposed over the source/drain component. A gate structure is disposed over the active region. The gate structure extends in a second horizontal direction different from the first horizontal direction. Side surfaces of the source/drain contact are substantially more tapered in the second horizontal direction than in the first horizontal direction.