Tapered Interposer Interconnects for Signal Integrity in HPC Packages
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Solution Overview
Problem
High-performance computing (HPC) semiconductor packages face issues with signal integrity and increased parasitics due to the high aspect ratio and length of column-shaped interconnect structures formed using a through-silicon via (TSV) process, which also consume excessive space in computing systems.
Innovation Solution
The use of tapered interconnect structures formed using a laser plug process reduces the thickness and aspect ratio of the interposer, improving signal integrity and reducing parasitics, while minimizing the overall package thickness and space consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If column-shaped interconnect structures are formed using TSV process, then electrical connectivity is achieved, but signal integrity deteriorates and parasitics increase due to high aspect ratio and length
Solution Approach 1:
The patent applies curvature by transitioning from straight column-shaped interconnect structures to tapered interconnect structures with angled sidewalls. This curved/tapered geometry reduces the effective electrical path length while maintaining structural integrity, thereby improving signal integrity and reducing parasitic effects associated with long straight vias.
Solution Approach 2:
The patent changes the geometric parameters of the interconnect structures by forming tapered vias with controlled aspect ratios instead of high aspect ratio columnar vias. This parameter change optimizes the balance between mechanical strength and electrical performance, reducing inductance and resistance while maintaining reliable electrical connectivity.
2Reliability
If column-shaped interconnect structures are formed using TSV process, then electrical connectivity is achieved, but device complexity increases due to excessive space consumption
Solution Approach 1:
The patent modifies the interconnect structure geometry from vertical columns to tapered structures with optimized aspect ratios. This parameter optimization allows for reduced interposer thickness while maintaining adequate mechanical support and electrical connectivity, thereby reducing overall package volume and space consumption in computing systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The laser plug process enhances the performance of semiconductor packages by increasing signal integrity and reducing parasitics, thereby optimizing space utilization in computing systems.
Implementation Method 1
tapered interconnect structures formed using a laser plug process
Data Source
AI summary
Some implementations herein describe a semiconductor package. The semiconductor package, which may correspond to a high-performance computing semiconductor package, includes an interposer. The interposer includes tapered interconnect structures formed using a laser plug process. The tapered interconnect structures may include a length that is lesser relative to a length of the column-shaped interconnect structures formed using a through-silicon via process. Such a length reduces a thickness of the interposer and reduces a length of electrical connections through the interposer. In this way, a signal integrity may be increased and parasitics of the semiconductor package including the tapered interconnect structures may be reduced to increase a performance of the semiconductor package. Additionally, the reduced thickness of the interposer may reduce an overall thickness of the semiconductor package to save space consumed by the semiconductor package in a computing system.