Tapered Memory Structure Layout for Faster Semiconductor Reads
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing load capacity and improving read time due to complex control mechanisms and structural limitations in their conductive layers and insulating layers.
Innovation Solution
The semiconductor memory device employs a tapered memory structure with a width that narrows with increasing distance from the substrate, and a source-side dividing insulating layer that separates conductive layers, allowing for reduced load capacity and improved read time by facilitating controlled access to memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional control mechanisms and structural designs are used in semiconductor memory devices, then device functionality is maintained, but load capacity increases and read time deteriorates
Solution Approach 1:
The patent divides the memory device into multiple banks (first bank, second bank, third bank) with independent control, allowing parallel access to different memory regions. This segmentation reduces the effective load on each bank and enables concurrent read operations, thereby reducing overall read time without requiring complex control logic within each bank
Solution Approach 2:
The patent introduces a new dimension of control by adding bank select signals that operate independently of word line and bit line control. This dimensional expansion allows the system to manage memory access in three dimensions (bank selection, word addressing, bit addressing) rather than two, enabling more efficient load distribution and faster read operations
2Ease of operation
If conventional conductive layer structures are used, then manufacturing processes are simpler, but access control to memory cells becomes less efficient
Solution Approach 1:
The patent implements different conductive layer configurations in different regions of the memory device. Specifically, the first conductive layer is positioned at different locations relative to the memory cells in different banks, allowing optimized local access control for each bank while maintaining overall manufacturing compatibility
Solution Approach 2:
The patent varies the physical parameters of the conductive layers, including their position, shape, and connection points, to optimize memory cell access control. By adjusting these parameters locally rather than using a uniform structure throughout, the device achieves improved access control while remaining compatible with standard manufacturing processes
3Quantity of substance
If memory devices are designed with higher capacity, then storage capability improves, but read time increases due to increased load capacity
Solution Approach 1:
The patent divides the high-capacity memory into multiple banks (first bank, second bank, third bank), each with its own set of memory cells and control structures. This segmentation allows the system to access different portions of the total capacity simultaneously through parallel bank operations, maintaining fast read times even as total memory capacity increases
Solution Approach 2:
The patent introduces bank select signals as intermediary control elements that route access requests to appropriate memory banks. These intermediary signals enable the control logic to efficiently manage high-capacity memory by directing operations to specific banks rather than treating the entire memory space as a single unit, thereby maintaining fast access times
Data Source
AI summary
A semiconductor memory device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a memory structure including a first semiconductor layer opposed to the first conductive layers, a first wiring, a second conductive layer, a first insulating layer separating the plurality of first conductive layers in a second direction, a second insulating layer separating one or a plurality of the first conductive layers disposed on a side closest to the substrate, and a third insulating layer separating one or a plurality of the first conductive layers disposed on a side farthest from the substrate. The memory structure has a tapered shape having a width in the second direction decreasing with increasing distance from the substrate, and the third insulating layer has a tapered shape having a width in the second direction decreasing with decreasing distance from the substrate.