Tapered Semiconductor Edge Design for LCD Transistor Reliability
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Solution Overview
Problem
The reliability of thin film transistors in liquid crystal display (LCD) devices is compromised due to strong electric fields and side currents caused by fringe field effects, leading to non-linear transfer curves and on/off time delays, which degrade the performance of the devices.
Innovation Solution
The implementation of a semiconductor layer with a tapered or multi-step edge portion design, where the edge surface has a reduced thickness, improves step coverage of the gate insulating layer and gate electrode, reducing fringe field effects and side currents, thereby ensuring normal drain current flow and enhancing transistor reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a semiconductor layer with uniform thickness is used, then the manufacturing process is simple, but strong electric fields and side currents occur due to fringe field effects at the edge portions
Solution Approach 1:
The semiconductor layer is designed with different thicknesses at different locations: the edge portions have a first thickness while the central portion has a second thickness. This local variation in thickness creates corresponding variations in the gate insulating layer thickness, which in turn creates different electric field strengths in different regions. The thinner edge portions generate weaker electric fields, suppressing fringe field effects and side currents, while maintaining adequate thickness in the central region for proper transistor operation.
2Device complexity
If the gate insulating layer thickness is uniform, then the device structure is simple, but fringe field effects cause non-linear transfer curves and on/off time delays
Solution Approach 1:
The gate insulating layer is designed with non-uniform thickness that corresponds to the semiconductor layer thickness variation. The edge portions have a first thickness while the central portion has a second thickness. This local thickness variation in the gate insulating layer creates corresponding variations in electric field strength, where the thinner edge regions produce weaker electric fields that suppress fringe field effects, ensuring linear transfer curves and proper on/off timing.
3Ease of manufacture
If the semiconductor layer edge portions have the same thickness as the center, then the fabrication process is straightforward, but side currents flow along the channel width due to strong electric fields
Solution Approach 1:
The semiconductor layer is designed with different thicknesses at the edge portions compared to the central portion. The edge portions have a first thickness while the center has a second thickness. This creates corresponding thickness variations in the gate insulating layer, which generates different electric field strengths in different regions. The thinner edge portions create weaker electric fields that suppress the generation of side currents along the channel width.
4Reliability
If a tapered or multi-step edge portion design is implemented, then step coverage is improved and fringe field effects are reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The semiconductor layer is designed with different thicknesses at the edge portions compared to the central portion, creating a tapered or multi-step profile. This local thickness variation improves step coverage of the gate insulating layer and gate electrode by providing gradual transitions, while simultaneously reducing fringe field effects through weakened electric fields at the edges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces fringe field-induced side currents, prevents humps in the transfer curve, and improves the reliability of thin film transistors by maintaining linear drain current response, thus enhancing the overall performance of the LCD devices.
Implementation Method 1
a gate insulating layer covering the semiconductor layer; a gate electrode on the gate insulating layer
Implementation Method 2
source and drain electrodes contacting the semiconductor layer
Implementation Method 3
a pixel electrode contacting the drain electrode
Data Source
AI summary
A liquid crystal display device may comprise a semiconductor layer on a substrate and including a channel portion and ohmic contact portions at both sides of the channel portion, wherein an edge portion of the semiconductor layer has a side surface of a substantially tapered shape; a gate insulating layer covering the semiconductor layer; a gate electrode on the gate insulating layer and substantially corresponding to the channel portion; source and drain electrodes contacting the semiconductor layer; and a pixel electrode contacting the drain electrode.