Tapered Sidewall Structure for Embedded Memory Isolation
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Solution Overview
Problem
The integration of embedded memory devices with logic devices in integrated circuits faces challenges due to the exposure of high κ dielectric material during processing, which can lead to contamination and affect doping levels, requiring a method to form smooth-surfaced tapered sidewall structures to prevent such exposure.
Innovation Solution
A method involving the formation of a tapered sidewall structure on the dummy gate stack, which includes a dummy gate dielectric layer and a dummy gate electrode layer, spaced above the isolation structure, allowing for an aggressive etch process without damaging the logic region, and using a spacer material to create a smooth surface during high κ dielectric deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an aggressive etch process is used to form the tapered sidewall structure, then manufacturing efficiency is improved, but the risk of damaging the logic region increases
Solution Approach 1:
The dummy gate stack is formed in advance on the isolation structure before the aggressive etch process. This preliminary structure serves as a protective template that guides the etch process, allowing aggressive etching conditions to be used while the dummy gate stack prevents damage to the underlying logic region. The dummy gate stack is removed later in the process after it has served its protective function.
Solution Approach 2:
The dummy gate stack acts as an intermediary protective layer between the aggressive etch process and the logic region. It absorbs the harsh etching conditions and protects the sensitive logic region underneath, enabling the use of aggressive etchants that would otherwise damage the logic region directly.
2Manufacturing precision
If the high κ dielectric material is exposed during processing, then deposition coverage is improved, but contamination occurs and doping levels are affected
Solution Approach 1:
The tapered sidewall structure is formed in advance to create a smooth, continuous surface that prevents high κ dielectric material exposure during subsequent processing. This preliminary protective geometry eliminates the crevices where material exposure and contamination would occur, allowing aggressive etching without compromising material containment.
Solution Approach 2:
The tapered sidewall structure creates a smooth curved surface profile instead of sharp corners or crevices. This curvature eliminates dead zones where high κ dielectric material could be exposed or contaminated, ensuring continuous material coverage and preventing contamination while maintaining good deposition coverage.
3Reliability
If a smooth-surfaced tapered sidewall structure is formed, then high κ dielectric containment is improved, but the device structure becomes more complex
Solution Approach 1:
The dummy gate stack, which creates the tapered sidewall structure, is a temporary structure that is removed after serving its protective function. By extracting this temporary structure, the patent achieves smooth tapered sidewalls for high κ dielectric containment without permanently increasing device complexity. The complex structure exists only temporarily during manufacturing.
Solution Approach 2:
The dummy gate stack is discarded after it has served its purpose of creating the tapered sidewall structure. This temporary structure is removed in a subsequent etch process, leaving behind the desired smooth tapered sidewalls without the complexity of the dummy structure. The temporary complexity is recovered by removing the dummy gate stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The tapered sidewall structure prevents contamination by ensuring the high κ dielectric is contained, protecting the logic region during processing and maintaining uniform doping levels, thereby enhancing the manufacturing efficiency and performance of integrated circuits.
Implementation Method 1
The tapered sidewall structure prevents contamination by ensuring the high κ dielectric is contained
Implementation Method 2
using a spacer material to create a smooth surface during high κ dielectric deposition
Data Source
AI summary
An integrated circuits device includes a semiconductor substrate having a logic region and a memory region separated by an isolation region having an isolation structure of dielectric material. A memory device is formed on the memory region and includes a gate electrode over a gate dielectric. A dummy gate structure is formed on the isolation structure. The dummy gate structure has a dummy gate electrode layer corresponding to the gate electrode and a dummy gate dielectric layer corresponding to the gate dielectric. A tapered sidewall structure is formed on a logic region-facing side of the dummy gate structure. The tapered sidewall structure is spaced above the isolation structure and either adjacent to or contiguous with the dummy gate electrode layer.