Targeted Test Fail Injection for Memory Self-Test Validation
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Solution Overview
Problem
Existing memory devices lack a reliable method to validate the operation of self-test circuitry, which can lead to false indications of memory array health, as current validation techniques are inefficient and require extensive testing to identify defects.
Innovation Solution
Incorporating self-test circuitry that can intentionally fail specific addresses during a test procedure, allowing for validation of the self-test circuitry's operation by comparing accessed addresses with stored addresses, regardless of the data written, and performing repair operations based on these failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If self-test circuitry is added to validate memory array operation, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The self-test circuitry is integrated within the memory device structure, with test circuits nested among the memory array cells. The circuitry uses existing memory structures (rows, columns, sense amplifiers) as part of the test infrastructure, embedding validation functionality within the natural hierarchy of the memory device rather than adding completely separate external test equipment.
Solution Approach 2:
The self-test circuitry is designed to perform multiple functions: it can test the memory array for defects, validate the operation of repair circuits, and provide diagnostic information about the health of memory components. The same test infrastructure is used to verify both normal memory operation and the functionality of defect repair mechanisms, eliminating the need for separate specialized test circuits for each function.
2Reliability
If comprehensive testing procedures are implemented to identify all defects, then reliability is improved, but loss of time increases
Solution Approach 1:
The self-test circuitry performs preliminary validation of memory array operation immediately after manufacturing or before deployment. By conducting initial defect identification and repair validation early in the device lifecycle, the system establishes a baseline of memory health without requiring extensive prolonged testing, thereby reducing overall testing time while maintaining reliability.
Solution Approach 2:
The testing procedure is designed to quickly identify and flag defective addresses through rapid self-test operations. Once defects are identified, the system can skip extensive re-testing of known defective areas and focus validation efforts on repair circuit functionality, thereby accelerating the overall testing process while maintaining comprehensive validation where needed.
Data Source
AI summary
Methods, systems, and devices for targeted test fail injection are described. A memory device may include self-test circuitry configured to test one or more memory cells of a memory array. The self-test circuitry may be configured to store one or more addresses to fail during a test of the memory array based on an indication from a mode register of the memory device. The self-test circuitry may be configured to fail the stored one or more addresses regardless of the outcome of the test at the one or more memory addresses. For example, when an accessed address matches a stored address during test, the self-test circuitry may generate an indication that the accessed address has failed one or more tests of the self-test procedure. Based on the self-test circuitry failing the stored addresses, a test of the memory array may be validated.