TDC Calibration in Digital PLLs Using DSM Quantization Error
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Solution Overview
Problem
Phase-locked loops (PLLs), particularly digital PLLs, face challenges in managing spot phase noise and stability due to process-voltage-temperature (PVT) variations, which affect bandwidth control and can lead to failure in meeting stringent noise requirements in applications like communication and Bluetooth low energy systems.
Innovation Solution
The implementation of a TDC calibration method that applies a gain adjustment factor based on a phase error signal and a test signal representing quantization error, allowing for direct gain control of the TDC, thereby reducing PVT variations' impact on bandwidth and ensuring stable phase noise performance without increasing the complexity or cost of the analog part.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If TDC gain is controlled to manage spot phase noise and bandwidth, then phase noise performance is improved, but PVT variations cause instability and measurement precision deteriorates
Solution Approach 1:
The patent performs TDC calibration in advance before normal PLL operation to determine and store calibration data that compensates for PVT variations. This preliminary calibration action ensures that the TDC gain is pre-adjusted to account for expected variations, thereby improving measurement precision while maintaining reliability during subsequent operation without requiring real-time adjustments
Solution Approach 2:
The patent implements a feedback mechanism where the calibrated TDC gain information is fed back into the PLL control loop. The calibration data obtained from measuring the relationship between TDC output and actual phase difference is used to adjust the TDC gain dynamically or statically, ensuring that phase noise measurements remain accurate despite PVT variations affecting system stability
2Measurement precision
If additional components are added to control TDC gain and bandwidth, then phase noise performance is improved, but device complexity increases
Solution Approach 1:
The patent enables the TDC to calibrate itself using its own output signals and the PLL's feedback mechanism. The TDC performs self-calibration by analyzing the relationship between its digital output codes and the actual phase difference measured through the PLL loop, eliminating the need for external calibration equipment or additional analog components. This self-service approach improves measurement precision while keeping device complexity low
Solution Approach 2:
The patent makes the TDC perform multiple functions: it serves as both the phase detection element during normal operation and as the calibration instrument for its own gain adjustment. The same TDC circuitry used for phase measurement is also used to generate calibration data and determine the appropriate gain adjustment, thereby improving measurement precision without adding dedicated calibration components
Data Source
AI summary
A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.