Temporal Addressing for Transient Operand Storage in Processors
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Solution Overview
Problem
Computer processors face challenges in efficiently managing transient operands due to the limitations of general register machines, including increased complexity, entropy, and power requirements, while alternative architectures like accumulator and stack machines are less performant due to sequential execution and limited parallelism.
Innovation Solution
A computer processing system with a fixed-length queue logically organized by temporal addresses, allowing operands to be produced and consumed in a single cycle, and featuring a bypass network that routes operands directly from producers to consumers without the need for registers, thereby optimizing operand handling and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of registers is increased to hold more transient operands, then access speed to operands is improved, but device complexity and instruction entropy increase
Solution Approach 1:
The patent extracts the transient operand storage function from the general register file, creating a separate dedicated storage structure. This allows the register file to maintain a manageable size for fast access while the extracted transient storage handles the volume of temporary operands, resolving the contradiction between speed and complexity.
Solution Approach 2:
The patent segments the operand storage system into distinct components: a compact register file for frequently accessed operands and a separate transient operand storage structure for short-lived intermediates. This segmentation allows each component to be optimized independently, maintaining fast access while reducing overall device complexity.
2Speed
If the number of registers is increased to hold more transient operands, then access speed to operands is improved, but instruction entropy increases
Solution Approach 1:
The patent extracts transient operand management from the instruction encoding scheme, using a separate storage structure with implicit addressing. This removes the need to encode large register numbers in instructions, reducing instruction entropy while maintaining fast access through the dedicated transient storage.
Solution Approach 2:
The patent introduces an intermediary transient operand storage structure that mediates between functional units and the register file. This intermediary handles transient operands with implicit temporal addressing, reducing the information content required in instructions while preserving fast access paths.
3Device complexity
If accumulator or stack machine architecture is used to manage transient operands, then device complexity is reduced, but execution becomes sequential and parallelism is limited
Solution Approach 1:
The patent creates a universal transient operand storage structure that serves multiple functional units simultaneously, enabling parallel access patterns. Unlike sequential accumulator or stack architectures, this structure allows multiple consumers to access different transient operands in parallel while maintaining a simple, unified design.
Solution Approach 2:
The patent transitions from the sequential one-dimensional access pattern of stacks and accumulators to a multi-dimensional addressing scheme that allows parallel access from multiple functional units. This dimensional change enables both reduced complexity and improved parallelism by allowing simultaneous operations on different transient operands.
Data Source
AI summary
A computer processor including a plurality of storage elements logically organized as a fixed length queue referenced by logical temporal addresses. The fixed length queue operates over multiple cycles to temporarily store operands referenced by at least one instruction utilizing the logical temporal addresses. A plurality of functional units performs operations over the multiple cycles, wherein the operations produce and access operands stored in the logical fixed length queue. Operands can be added to the front of the logical fixed length queue according to the temporal order that operands are produced by the functional units, and operands can drop from the end of the logical fixed length queue as operands are added to the front of the fixed length queue. A plurality of operands produced by the plurality of functional units (possibly with different latencies in producing such operands) can be added to the logical fixed length queue in a single cycle. A plurality of operands operated on by the functional units can be accessed from the logical fixed length queue in a single cycle.