Ternary Neural Network Accelerator Using Dual-Threshold Memory Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing neural network accelerators optimized for binary processing suffer from low calculation accuracy due to processing only binary data.
Innovation Solution
A ternary neural network accelerator device utilizing ferroelectric field effect transistors (FeFET) or flash memory devices with dual threshold voltages and voltage combinations on searching lines to process ternary data, enabling nine computation results through a simple structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If binary neural network accelerators are used for lightweight processing, then device complexity is reduced, but calculation accuracy deteriorates
Solution Approach 1:
The patent changes the data representation parameter from binary (0,1) to ternary (-1,0,1) to improve calculation accuracy while maintaining the lightweight network structure. This parameter change allows the neural network to process three states instead of two, enhancing the precision of weight representation and computational results without increasing the fundamental architectural complexity
2Measurement precision
If ternary data processing is implemented, then calculation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the processing into two distinct operations: a first operation that sets threshold voltages to ternary states, and a second operation that applies voltage combinations to searching lines. This segmentation allows complex ternary processing to be broken down into manageable steps, reducing the perceived device complexity while maintaining high calculation accuracy
Solution Approach 2:
The patent makes the existing neural network accelerator structure universal by enabling it to handle both binary and ternary data formats through configurable threshold voltages and voltage combinations. This multi-functionality allows the same hardware architecture to perform accurate ternary processing without requiring a completely new device design, thus avoiding increased device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances calculation accuracy while maintaining a lightweight network architecture by processing ternary data, improving performance without increasing complexity.
Implementation Method 1
utilizing ferroelectric field effect transistors (FeFET) or flash memory devices with dual threshold voltages
Implementation Method 2
a first threshold voltage of the first semiconductor device and a second threshold voltage of the second semiconductor device is changed to one of three states obtained by combining a relatively low threshold voltage and a relatively high threshold voltage
Implementation Method 3
nine computation results are output through the matching line according to conditions of the ternary weight and ternary input
Data Source
AI summary
According to one aspect of the present invention, a ternary neural network accelerator device includes a first semiconductor device comprising a first source terminal, a first drain terminal, and a first gate terminal, a second semiconductor device comprising a second source terminal, a second drain terminal, and a second gate terminal, a first searching line connected to the first drain terminal, a second searching line connected to the second drain terminal, and a matching line commonly connected to the first source terminal and the second source terminal, wherein ternary weight and ternary input are each set by either of a first operation and a second operation and nine computation results are output through the matching line according to conditions of the ternary weight and ternary input.