Tessellation Redistribution Bus for GPU Geometry Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In graphics processing units (GPUs), increasing the number of geometry processing pipelines (GPPs) leads to performance degradation due to the need for deeper buffers to manage output buffering, which can result in stalled pipelines and reduced geometry throughput if sufficient buffering is not provided.
Innovation Solution
Implementing a local tessellation work redistribution mechanism that allows for direct distribution of patches across tessellation stages without off-chip memory access, using a Tessellation Redistribution Bus (TRB) to maintain sequential ordering and avoid buffer stalls, thereby enhancing tessellation processing rate and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of GPPs is increased to improve parallel rendering performance, then geometry processing throughput is improved, but deeper buffers are required which increases device complexity and may cause pipeline stalls
Solution Approach 1:
The patent segments the geometry processing workflow by separating tessellation control shader (TESC) execution from tessellation evaluation shader (TEVAL) execution across different GPPs. TESC results are redistributed to appropriate TEVAL units via a tessellation redistribution bus, allowing independent parallel execution and eliminating the need for deep buffering between stages.
Solution Approach 2:
The patent introduces a tessellation redistribution bus as an intermediary mechanism between TESC and TEVAL stages. This bus enables direct redistribution of tessellation control results to waiting TEVAL units without requiring large on-die buffers, thus resolving the buffering complexity issue while maintaining high throughput.
2Productivity
If deeper buffers are provided to prevent pipeline stalls, then geometry throughput is maintained, but power consumption increases due to larger buffer memory
Solution Approach 1:
By segmenting the tessellation pipeline into separate TESC and TEVAL stages that can operate independently and in parallel, the patent eliminates the need for large buffering infrastructure. This reduces the memory power consumption while maintaining continuous geometry throughput through efficient redistribution of work between stages.
3Reliability
If larger on-die buffers are used to manage GPP output buffering, then pipeline stalls are avoided, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the geometry processing pipeline so that TESC and TEVAL operations are performed by separate GPPs. This segmentation allows results to be redistributed directly from one GPP to another without requiring large intermediate buffers, thus maintaining pipeline continuity while reducing buffer requirements and device complexity.
Solution Approach 2:
The tessellation redistribution bus serves as an intermediary that enables direct communication and data transfer between TESC and TEVAL GPPs. This eliminates the need for large on-die buffers while ensuring reliable pipeline operation through efficient work redistribution.
Data Source
AI summary
The tessellation processing rate of a graphics processor may be increased using of local tessellation work redistribution. The redistribution mechanism may avoid the need for large on-die buffers and, as the distribution is local, the performance and power penalty incurred by use of off-chip memory accesses may also avoided in some embodiments.