Test Access Port Circuit Parallel Data Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing JTAG test access port circuits have low data transmission throughput due to serial data output and input, requiring additional hardware to increase speed and limiting system flexibility.
Innovation Solution
A test access port circuit with a controller that manages multiple register sets and mode selection signals to enable parallel data input and output through both data and reset terminals, utilizing auxiliary registers to double or triple the transmission rate without altering the finite state machine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted through the JTAG interface in a serial manner, then the system maintains simplicity and uses standard interfaces, but the transmission rate is very low
Solution Approach 1:
The patent divides the data transmission function into multiple parallel channels by utilizing both the data input terminal and reset terminal for simultaneous data input, and both data output terminal and reset terminal for simultaneous data output. This segmentation of the single serial channel into multiple parallel channels increases the transmission rate without requiring additional external hardware interfaces
Solution Approach 2:
The reset terminal is given dual functionality: it serves both as a reset control signal terminal and as a data input/output terminal. The controller selectively responds to reset signals based on mode selection signals, allowing the same physical terminal to perform multiple functions including resetting the controller and transmitting data bits in parallel with other terminals
2Speed
If additional hardware is added to increase data transmission speed, then the transmission rate improves, but the flexibility of the test system becomes very limited
Solution Approach 1:
The controller dynamically adjusts its operation based on mode selection signals, switching between different operational modes (reset terminal input mode, data input terminal input mode, data output terminal output mode, reset terminal output mode) to optimize data transmission. This dynamic adaptability allows the system to achieve higher transmission speeds through parallel operations while maintaining the flexibility to respond to different testing requirements through software/control signal configuration rather than fixed hardware
Data Source
AI summary
A test access port circuit includes a data input terminal, a reset terminal, a mode selection terminal, at least one test data register set, an auxiliary data register set, an instruction register set, and a controller. The controller is coupled to the mode selection terminal and the instruction register set, and controls the at least one test data register set, the auxiliary data register set, and the instruction register set according to at least mode selection signal received by the mode selection terminal. In a reset terminal input mode, when the controller controls a test data register set of the at least one test data register set to store a first input data bit received by the data input terminal, the auxiliary data register set stores a second input data bit received by the reset terminal.