Test Control Circuit for Semiconductor Memory Erase Testing
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Solution Overview
Problem
Existing erase test methods for semiconductor memory devices face challenges in efficiently managing failed cells, leading to variations in test time and excessive application of erasure voltage, which can affect the reliability and efficiency of the testing process.
Innovation Solution
A test control circuit with an address sequencer, register, selector, and verify determination circuit that selectively applies a predetermined voltage to cells based on their failure status, allowing for a first and second verify determination, thereby reducing the influence of failed cells and minimizing loop formation in address sequencing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the erase test is performed again after returning to the stored address in the address sequencer, then the influence of the failed cell is reduced, but variations in test time occur due to address loops
Solution Approach 1:
The patent stores the address of the first failed cell in advance during the initial verification pass. This stored address is then used in a subsequent verification pass to skip already-tested failed cells, preventing address loops and reducing test time variations while maintaining reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the address sequencer uses the stored failed cell address information to adjust its addressing sequence. The address generator modifies subsequent addressing based on feedback from the verification results, eliminating redundant testing of the same failed cells and stabilizing test time.
2Reliability
If a predetermined voltage for erasure is applied only when fails are determined in multiple groups, then the reliability of erasure is improved, but the test process becomes more complex
Solution Approach 1:
The patent segments the memory cell array into multiple groups and performs verification on each group separately. This segmentation allows the system to track failed cells in different groups independently and apply erasure voltage selectively, improving erasure reliability while managing complexity through structured organization.
Solution Approach 2:
The patent implements dynamic control of the erasure voltage application based on real-time verification results. The test control circuit dynamically determines when to apply erasure voltage by monitoring fail patterns across multiple groups, adjusting the erasure process adaptively rather than using a fixed approach.
Data Source
AI summary
Disclosed herein are test control circuit, semiconductor memory device, and testing method embodiments for suppressing variations in test time while reducing the influence of a failed cell. An embodiment operates by performing a first verify of a cell selected in a predetermined order; storing an address of the cell when the first verify is a fail until the number of addresses is a predetermined number; applying a predetermined voltage to a plurality of cells of an erase unit when a next fail is determined in the first verify after the predetermined number of addresses have been stored; and performing a second verify to one or more cells indicated by the predetermined number of addresses, wherein the first verify is performed from a cell at the next fail according to the predetermined order after the second verify has finished.