Test-Enabled Flip-Flop Register for Low-Delay Scan Paths
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Solution Overview
Problem
Existing semiconductor testing methodologies introduce significant delay due to the increased propagation time associated with the number of test modes, which is problematic for high clock frequency devices.
Innovation Solution
The implementation of test enabled flip-flops with a test mode input signal and a test circuit that includes gated inverter circuits, allowing for minimal propagation delay by selectively gating the clock input and providing a test data input signal when the test mode is asserted, thereby reducing the overall delay in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple test modes are implemented using multiplexers, then testing capability is improved, but propagation delay increases
Solution Approach 1:
The patent segments the test mode selection functionality from the data path by implementing dedicated test mode inputs directly at the flip-flop level. This segmentation allows test mode selection to occur independently without requiring signals to traverse through multiple multiplexer stages, thereby reducing propagation delay while maintaining the ability to select from multiple test modes.
Solution Approach 2:
The patent introduces an intermediary test mode input signal that directly controls the flip-flop's operation mode. This intermediary signal acts as a mediator between the test control logic and the flip-flop, enabling test mode selection without requiring the test signal to pass through the data multiplexer path, thus eliminating the cumulative delay of multiple multiplexer stages.
2Adaptability or versatility
If test multiplexers are added to core logic, then test functionality is improved, but device complexity increases
Solution Approach 1:
The patent merges the test mode selection functionality directly into the flip-flop structure by adding test mode inputs at the flip-flop level. This integration eliminates the need for separate test multiplexers in the core logic, as the flip-flop itself becomes capable of mode selection. The merging reduces device complexity by removing redundant multiplexer components while maintaining comprehensive test functionality.
Solution Approach 2:
The patent enhances the universality of the flip-flop by making it multi-functional: it can operate in both normal data registration mode and various test modes directly controlled by its inputs. This multi-functionality eliminates the need for separate dedicated test multiplexers, as the flip-flop itself can handle both operational modes, thereby reducing overall device complexity while maintaining test functionality.
3Reliability
If standard multiplexer testing paths are used, then test coverage is improved, but operational frequency is limited
Solution Approach 1:
The patent applies preliminary action by pre-configuring the flip-flop with direct test mode inputs that enable test signal injection at the register stage. This preliminary configuration allows test signals to bypass the normal data path multiplexers, establishing a direct test path that does not add propagation delay. As a result, test coverage is maintained while the critical data path can operate at higher frequencies without being constrained by test multiplexer delay.
Data Source
AI summary
Various systems and methods for registering data are disclosed herein. For example, test enabled flip-flop devices are provided. Such devices include a test mode input signal and a register output signal. In addition, the devices include a flip-flop with a data input and a clock input. When the test mode input signal is de-asserted, the flip-flop is operable to register the data input upon a transition of the clock input. Further, the registered data input signal is provided as the register output signal. The devices also include a test circuit with a test data input. The test circuit is operable to provide the test data input signal as the register output signal when the test mode input signal is asserted.