Test Mode Setting Circuit Voltage Reset Signal Latching
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Solution Overview
Problem
Existing test mode setting circuits in semiconductor devices cannot maintain an activated test mode signal during supply voltage reset, preventing test mode operations from being performed after mode setting is completed.
Innovation Solution
A test mode setting circuit with a first test mode signal generation unit that activates a test mode signal at a first voltage level during mode setting and a second test mode signal generation unit that latches and maintains the signal at a second voltage level even when the first supply voltage is reset, allowing the test mode to be set and maintained after the initial mode setting is completed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the test mode setting circuit uses a single supply voltage for operation, then the circuit structure is simple, but the test mode signal cannot be maintained during supply voltage reset
Solution Approach 1:
The test mode setting circuit is divided into two independent signal generation units: a first test mode signal generation unit operating at a first voltage level and a second test mode signal generation unit operating at a second voltage level. This segmentation allows each unit to operate independently during different phases (mode setting vs. test operation), enabling the test mode signal to be maintained even when the first supply voltage is reset.
2Productivity
If the test mode setting circuit maintains signal state during voltage reset, then test operations can be performed after reset, but the circuit complexity increases
Solution Approach 1:
The first test mode signal generation unit activates the test mode signal in advance during the mode setting phase before the supply voltage is reset. This preliminary action ensures that the test mode is already configured and ready to be maintained by the second signal generation unit when the reset occurs, enabling continuous test operations without interruption.
Solution Approach 2:
The second test mode signal generation unit acts as an intermediary that receives the test mode signal from the first unit during normal operation and maintains it during supply voltage reset. This intermediary unit bridges the gap between the mode setting phase and the test operation phase, ensuring signal continuity despite the voltage reset.
3Ease of operation
If the test mode is set only during mode setting phase, then the circuit operation is simple, but test operations cannot be performed after supply voltage reset
Solution Approach 1:
The circuit ensures continuous test mode signal availability by having the first signal generation unit operate during mode setting and the second signal generation unit take over during test operations after reset. This continuity of useful action eliminates gaps in test operation availability, allowing test modes to be performed both before and after supply voltage reset without interruption.
Data Source
AI summary
A test mode setting circuit may include: a first test mode signal generation unit operated by a first supply voltage, and suitable for activating a first test mode signal at a first voltage level in a state where mode setting is being performed, the first test mode signal corresponding to a test code among a plurality of first test mode signals; and a second test mode signal generation unit operated by a second supply voltage, and suitable for latching the first test mode signal at a second voltage level and generating the latched first test mode signal as a second test mode signal even when the first supply voltage is deactivated to a third supply voltage lower than the first supply voltage.