Test Pattern Generating Circuit for High-Speed Memory Testing
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Solution Overview
Problem
Conventional test equipment for semiconductor memory devices is unable to generate test patterns at the high speeds required for contemporary high-speed semiconductor memory devices, due to the use of techniques like DDR, QDR, and ODR, which restricts precise testing capabilities.
Innovation Solution
A test pattern generating circuit that synchronizes low-frequency external clock signals with high-frequency internal clock signals to load and unload test patterns, allowing for the generation of varying types and lengths of test patterns, enabling precise testing of semiconductor memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional low-speed test equipment is used to test high-speed semiconductor memory devices, then the test equipment can operate with existing capabilities, but the testing speed is insufficient to match the data transmission speed of the devices
Solution Approach 1:
The test pattern generating circuit is divided into multiple register blocks (first, second, third, fourth register blocks) that can be independently controlled. Each register block can be selectively activated based on the required test pattern length, allowing the circuit to generate test patterns of varying lengths (e.g., 8-bit, 16-bit, 24-bit, 32-bit) to match different data transmission speeds and test requirements.
Solution Approach 2:
The circuit employs dynamic control mechanisms including a register block control unit that selectively activates specific register blocks based on test requirements. The circuit can dynamically adjust its operation mode between loading test signals from external equipment and generating test patterns internally, and can vary the test pattern length dynamically to match different testing scenarios and speed requirements.
2Adaptability or versatility
If the test pattern length is fixed, then the circuit design is simpler, but the range of test patterns is insufficient for comprehensive testing
Solution Approach 1:
The test pattern generating circuit is divided into multiple register blocks (first, second, third, fourth register blocks) that can be independently controlled. Each register block can be selectively activated based on the required test pattern length, allowing the circuit to generate test patterns of varying lengths (e.g., 8-bit, 16-bit, 24-bit, 32-bit) to match different data transmission speeds and test requirements.
Solution Approach 2:
The circuit is designed to perform multiple functions: it can load test signals from external test equipment, generate test patterns internally using multiple register blocks, and output test patterns of various lengths through selective activation of different register blocks. This multi-functional design provides versatility without requiring separate circuits for different test scenarios.
3Speed
If test signals are loaded at low external clock frequency, then synchronization with external equipment is easier, but the test patterns cannot be provided at the high speeds required by modern memory devices
Solution Approach 1:
The circuit loads test signals from external test equipment at a low external clock frequency during a preliminary loading phase, allowing for easy synchronization with the external equipment. Once loaded, these test signals are stored in the register blocks and then unloaded as test patterns at the high internal clock frequency required by modern memory devices. This preliminary loading action separates the synchronization requirement from the high-speed operation requirement.
Solution Approach 2:
The register blocks serve as an intermediary storage mechanism between the low-speed external test equipment and the high-speed memory device under test. Test signals are loaded into the register blocks at low speed for easy synchronization, then these stored signals are unloaded at high speed to match the memory device's data transmission rate, effectively mediating between the two different speed domains.
Data Source
AI summary
Provided are a test pattern generating circuit which generates test patterns having various types and lengths and a semiconductor memory device which performs a test operation using the test pattern generating circuit. The test pattern generating circuit includes a plurality of register blocks which receive test signals input from an external tester through an input/output pad and load the test signals into the resister blocks in synchronization with a low-frequency clock signal; a register block control unit which controls the activation of the register blocks; and an output unit which is connected to the register blocks and outputs the signals loaded into the register blocks as test patterns in synchronization with a high-frequency clock signal.