Test Pattern Generator Reducing Overlap via History Storage
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Solution Overview
Problem
As memory systems evolve with increased command sets and banks, the number of test patterns required for verification grows exponentially, leading to increased test time and high probabilities of test pattern overlap, resulting in saturated test coverage.
Innovation Solution
A test pattern generator that includes a random command address generator, an address converter, a history storage circuit, and a controller to classify and manage command and address combinations, preventing redundant testing by checking for 'no hit' conditions in the history storage circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test patterns are randomly generated to verify memory with increased command sets and banks, then test coverage increases, but test time increases exponentially and test pattern overlap increases
Solution Approach 1:
The patent applies preliminary action by checking the history storage circuit before generating test patterns. The controller checks whether a command-address combination has been previously tested by accessing the history storage circuit with the converted address. If the history indicates the combination has been tested (hit), the controller generates a new combination. This preliminary check prevents redundant testing and reduces test time while maintaining comprehensive test coverage.
2Reliability
If test patterns are randomly generated for extended test duration, then more command sets and banks are covered, but probability of test pattern overlap increases
Solution Approach 1:
The patent implements feedback by continuously monitoring test results and updating the history storage circuit. After testing a command-address combination, the controller updates the history storage circuit to mark that combination as tested. Subsequent random generation uses this feedback information to avoid selecting already-tested combinations, thereby reducing test pattern overlap while extending test duration for comprehensive coverage.
3Adaptability or versatility
If more command sets and banks are added to memory, then memory capacity and functionality increase, but number of test patterns required increases exponentially
Solution Approach 1:
The patent applies dimensionality change by converting the two-dimensional command-address combinations into a one-dimensional address space for the history storage circuit. The address converter maps multiple command-address combinations to a compact history address, allowing efficient storage and retrieval of test history. This dimensional transformation enables the system to track and manage a large number of test patterns for expanded memory functionality without exponential increase in complexity.
Data Source
AI summary
A test pattern generator includes a random command address generator suitable for generating N combinations, each combination of a command and an address, where N is an integer greater than or equal to 2; an address converter suitable for converting the N combinations into an N-dimensional address; a history storage circuit which is accessed based on the N-dimensional address; and a controller suitable for classifying the N combinations as issue targets, when an area in the history storage circuit, which is accessed based on the N-dimensional address, indicates a value of no hit.