Test Signal Distribution Circuit for Parallel Probe Testing
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Solution Overview
Problem
The increasing number of connection pins in electronic devices complicates parallel testing on silicon wafers, as existing test systems are limited by the number of probes required, and replicated pads for signal distribution can cause synchronization issues and propagation delays, limiting the number of chips that can be tested simultaneously.
Innovation Solution
A test signal distribution circuit with a 'master' buffer and 'slave' buffers connected via an interconnection bus is used to replicate test signals internally during testing, while disabling the circuit for normal operation to avoid propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If replicated pads are used for signal distribution to different circuits, then signal speed is improved, but the number of probes required increases
Solution Approach 1:
The patent merges multiple replicated pads into a single pad during test operations by using an internal connection mechanism. The test signal applied to one pad is distributed to multiple circuits through internal routing, eliminating the need for separate probes on each replicated pad while maintaining signal distribution functionality.
Solution Approach 2:
The patent implements dynamic reconfiguration of pad connections based on operational mode. During testing, replicated pads are internally connected to reduce probe requirements. During normal operation, the connections are reconfigured to provide independent signal paths for maximum speed. This dynamic switching resolves the contradiction between probe count and signal speed.
2Adaptability or versatility
If the number of connection pins is increased to support more functions, then device functionality is improved, but testing time increases
Solution Approach 1:
The patent reduces the effective number of pins requiring testing by merging replicated pads into a single test access point. This internal consolidation allows multiple functions to be tested through fewer probes, significantly reducing testing time while maintaining full device functionality.
Solution Approach 2:
The patent makes a single pad serve multiple functions by enabling it to distribute test signals to multiple circuits internally. This multi-functional approach allows one pad to replace multiple replicated pads during testing, reducing the testing burden while preserving the ability to test all device functions.
3Speed
If replicated pads are connected internally, then propagation delays are reduced, but synchronization problems occur during normal operation
Solution Approach 1:
The patent dynamically switches between two operational states: during testing, internal connections are activated to reduce propagation delays; during normal operation, the connections are deactivated or reconfigured to maintain proper signal synchronization. This temporal separation of functions resolves the contradiction between speed and reliability.
Solution Approach 2:
The patent implements periodic reconfiguration of the internal connections based on operational phase. The system alternates between test mode (with internal connections for speed) and normal operation mode (with independent paths for synchronization), ensuring that each mode operates under optimal conditions without compromising the other.
Data Source
AI summary
The circuit distributes a test signal applied to a pad of an electronic device that is enabled during test phases of the device and disabled during normal functioning. The circuit includes a “master” buffer, one or more “slave” buffers, one for each replicated pad, and an interconnection bus of the “master” and “slave” buffers. During a test phase, the “master” buffer replicates on the interconnection bus the test signal fed to a pad of the device, while the “slave” buffers convey to the various replica pads of the feed pad the signal present on the interconnection bus. During the normal operation of the device, the circuit remains disabled.