Tester I/O Port Multiplexing for Semiconductor Chip Testing
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Solution Overview
Problem
Existing semiconductor testers have a limited number of test ports, which restricts the ability to accelerate chip testing and increases manufacturing costs due to the need for more testers.
Innovation Solution
A test method where a single I/O port of a tester outputs duplicated test signals to multiple chips through a load board, with feedback signals generated by each chip being combined or averaged to determine normal operation, allowing each I/O port to test multiple chips simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more testers are used to accelerate chip testing, then chip production capacity is improved, but manufacturing cost increases
Solution Approach 1:
The patent makes a single tester's I/O port perform multiple functions by enabling it to simultaneously test multiple chips. The tester outputs test signals to multiple chips through a load board and collects feedback signals from all chips through the same I/O port, allowing one tester to replace multiple testers and thereby increase production capacity without proportionally increasing the number of testers.
Solution Approach 2:
The patent uses a load board to duplicate test signals from a single source to multiple chips. The test signal is copied and distributed to multiple chips simultaneously, enabling parallel testing. This signal duplication approach allows one tester to effectively become multiple testers, improving productivity while controlling the quantity of testing equipment needed.
2Quantity of substance
If a single I/O port tests multiple chips, then the number of testers is reduced, but signal management complexity increases
Solution Approach 1:
The patent introduces a load board as an intermediary device between the tester and multiple chips. The load board receives the test signal from the single I/O port, distributes it to multiple chips, and collects feedback signals from all chips. This intermediary handles the complex signal routing and management, isolating the tester from the complexity while enabling one-to-many testing connections.
Solution Approach 2:
The patent segments the testing function by separating the signal distribution and collection tasks from the tester itself and placing them in the load board. The load board is divided into multiple channels, each handling a specific chip's test signal path. This segmentation allows complex signal management to be handled in a modular way, reducing the burden on the tester's I/O port while maintaining the ability to test multiple chips simultaneously.
Data Source
AI summary
The present invention provides a test method, a tester, a load board and a test system. The test method includes: outputting, through a first input/output (I/O) port of a tester, a first test signal to a first channel of a load board, wherein the first test signal is used to generate a second test signal and a third test signal; receiving, through the first I/O port, a third feedback signal returned from the first channel, wherein the third feedback signal is generated based on a first feedback signal and a second feedback signal; and determining whether a first chip and a second chip are operating normally based on the third feedback signal. Solutions provided in the present invention are capable of increasing the number of chips that can be tested at a single time.