Testing Device With Segmented Program Counters

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Solution Overview

Problem

The increasing number of bits in program counter values for diversified testing processes requires a large number of wirings between the control substrate and pin electronics substrates, making it difficult to implement efficiently due to physical constraints in substrate mounting work.

Innovation Solution

A testing device configuration that includes a control substrate with a program counter and code analysis circuit, and pin electronics substrates with their own program counters, using reduced wiring by outputting control data based on instruction codes to adjust pin data output, allowing simultaneous testing of multiple pins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of bits of program counter values is increased to allow diversified testing processes, then the testing functionality and versatility are improved, but the number of wirings required between control substrate and pin electronics substrates increases significantly

Engineering Contradiction:
Improvetesting functionalityVSAvoidnumber of wirings
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the program counter functionality into two segments: a common program counter located in the control substrate that stores instruction codes, and local program counters in each pin electronics substrate that generate address signals. This segmentation allows the high-bit program counter values to be generated centrally and distributed through fewer wirings, while still enabling diversified testing processes through the instruction code memory architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an instruction code memory as an intermediary component between the common program counter and the pin electronics substrates. This intermediary stores the program counter values and generates address signals that are then sent to the pin electronics substrates, reducing the wiring requirement from direct high-bit connections to connections through this intermediate memory structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If more pin electronics substrates are provided to increase the number of testable pins, then the testing capacity is improved, but the physical mounting complexity and wiring difficulty increase

Engineering Contradiction:
Improvenumber of testable pinsVSAvoidsubstrate mounting work
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent implements a universal control substrate architecture with a common program counter and instruction code memory that serves all pin electronics substrates. This multi-functional design allows multiple pin electronics substrates to be controlled through shared resources (common program counter, instruction code memory), reducing the per-substrate wiring requirements and simplifying the mounting process while maintaining high testing capacity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the control functions by placing intelligence (program counters and instruction code memory) in the control substrate while keeping pin electronics substrates simpler. This segmentation allows the complex control logic to be centralized where it can be efficiently managed, while each pin electronics substrate remains a relatively simple unit that is easier to manufacture and mount.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9557384B2Testing device
Publication Date: 2017.01.31 RENESAS ELECTRONICS CORP
  • US9557384B2 patent drawing
  • US9557384B2 patent drawing
  • US9557384B2 patent drawing

AI summary

A testing device has plural pin electronics substrates and a control substrate. The control substrate includes a first instruction code memory storing an instruction code, a first program counter incrementing a count in synchronization with a clock, a code analysis circuit analyzing the instruction code read from the first instruction code memory in accordance with a counter value, and a control data output control circuit outputting control data for controlling the pin electronics substrates in accordance with the instruction code. Each pin electronics substrate includes a first pin memory storing pin data, a second program counter incrementing a count in synchronization with the clock, and a pin data output control circuit adjusting, based on control data, the count value of the second program counter and outputting pin data read from the first pin memory, the pin data being dependent on the count value of the second program counter.