Testkey Design Pattern for Gate Oxide Measurement
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Solution Overview
Problem
The measurement of gate oxide thickness is distorted due to exponentially increasing gate leakage current and series parasitic resistance as critical dimensions decrease, leading to errors in capacitance and oxide thickness extraction in advanced CMOS technology development.
Innovation Solution
A testkey design pattern featuring an n*m array of electronic devices with conductive contacts and parallel conductive lines, and a two-end-contact type design that reduces total resistance by forming multiple current paths, thereby minimizing measurement errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the critical dimension is decreased to scale down oxide thickness, then the oxide thickness extraction accuracy is improved, but the gate leakage current increases exponentially causing measurement distortion
Solution Approach 1:
The test structure is divided into multiple parallel conductive lines (first line, second line, third line, fourth line) with multiple pairs of sources and drains. This segmentation creates multiple measurement paths that can be combined to reduce the impact of gate leakage current on the overall measurement accuracy.
2Manufacturing precision
If the critical dimension is decreased to scale down oxide thickness, then the oxide thickness extraction accuracy is improved, but the series parasitic resistance increases causing measurement distortion
Solution Approach 1:
Multiple conductive lines and multiple pairs of sources and drains are merged in parallel to form a composite test structure. This merging reduces the total series parasitic resistance by providing multiple parallel current paths, thereby improving the accuracy of oxide thickness extraction despite the reduced critical dimensions.
3Measurement precision
If a smaller test pattern is used to reduce parasitic capacitance, then the measurement accuracy is improved, but the total capacitance value becomes too small causing undesirable error
Solution Approach 1:
Multiple conductive lines with multiple pairs of sources and drains are merged in parallel to achieve an optimal balance. This merging increases the total capacitance value to reduce measurement errors while maintaining relatively small individual device dimensions to minimize parasitic capacitance effects.
4Measurement precision
If the gate length is reduced to lower channel resistance, then the measurement accuracy is improved, but the gate length variation causes unacceptable error
Solution Approach 1:
Multiple pairs of sources and drains are merged in parallel to form the test structure. This merging reduces the total channel resistance while using a relatively larger effective gate length, thereby reducing sensitivity to gate length variation and improving measurement accuracy.
5Measurement precision
If multiple conductive contacts are used to reduce total resistance, then the measurement accuracy is improved, but the device complexity increases
Solution Approach 1:
The multiple conductive contacts serve dual functions: they reduce the total series parasitic resistance by providing parallel current paths, and they enable multiple measurement configurations. This multi-functionality justifies the increased structural complexity by delivering superior measurement accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed testkey design patterns significantly reduce measurement errors and enhance the accuracy of gate oxide thickness extraction without increasing calibration complexity or equipment costs.
Implementation Method 1
Because the electronic devices form an n*m array, they are an ensemble to reduce the total resistance for the parallel effect and therefore increase the accuracy of the measurement
Implementation Method 2
a plurality of parallel conductive lines of a first width vertically and electrically connected to the conductive contact
Data Source
AI summary
A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.