Thin Film Transistor Array Panel Halftone Mask Design
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Solution Overview
Problem
In thin film transistor array panels, the use of a single halftone mask for forming gate driving pad contact holes and semiconductor layers can lead to shorts between sustain and drain electrodes due to foreign particles or bubbles, resulting in a 'black dot' phenomenon, especially when the thickness of the halftone photosensitive film is less than 9000 Å.
Innovation Solution
A thin film transistor array panel design that includes a gate line, storage electrode line, gate driving pad, gate insulating layer, first and second semiconductor layers, data line, and pixel electrode, with the second semiconductor layer overlapping the sustain electrode to prevent shorts, and a manufacturing method that forms these layers using a halftone photosensitive film with varying exposers to ensure proper exposure and prevent foreign particle or bubble-induced shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single halftone mask is used to form gate driving pad contact hole and semiconductor layer, then manufacturing process is simplified and production costs are reduced, but foreign particles or bubbles greater than 9000 Å can cause holes exposing sustain electrode, resulting in short between sustain electrode and drain electrode
Solution Approach 1:
The patent segments the halftone mask into multiple thickness regions (first halftone region with thickness of 9000-15000 Å and second halftone region with thickness of 3000-9000 Å). This segmentation allows different regions to serve different functions: the first region prevents particle-induced shorts while the second region allows proper exposure, thus resolving the contradiction between manufacturing simplicity and electrical connection reliability.
Solution Approach 2:
The patent applies local quality by creating a halftone mask with spatially varying thickness. The first halftone region (thicker) is positioned over areas where particle-induced shorts are most likely to occur, providing enhanced protection. The second halftone region (thinner) is positioned in areas where proper exposure is critical. This local differentiation resolves the contradiction by optimizing both manufacturing ease and electrical reliability in different locations.
2Measurement precision
If the thickness of halftone photosensitive film is reduced to less than 9000 Å, then exposure precision is improved, but the film becomes vulnerable to foreign particles and bubbles, causing holes and electrode shorts
Solution Approach 1:
The patent changes the thickness parameter of the halftone mask to create a multi-region structure. By setting the first halftone region thickness to 9000-15000 Å and the second halftone region thickness to 3000-9000 Å, the patent optimizes both exposure precision and particle resistance. The thicker first region blocks particles while the thinner second region maintains exposure precision, resolving the contradiction between these two requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents the shorting of sustain and drain electrodes by using a second semiconductor layer to cover the sustain electrode, thereby preventing the 'black dot' defect and ensuring reliable electrical connections.
Implementation Method 1
forming a halftone photosensitive film including a first exposer, a second exposer that is thinner than the first exposer, and a third exposer for exposing the semiconductor layer
Data Source
AI summary
A thin film transistor array panel includes: a substrate including a display area and a drive region in which a driving chip for transmitting a driving signal to the pixels is located; a gate line in the display area; a storage electrode line; a gate driving pad coupled to the driving chip; a gate insulating layer; a first semiconductor layer on the gate insulating layer and overlapped with a gate electrode protruding from the gate line; a second semiconductor layer formed on the gate insulating layer and overlapped with a sustain electrode protruding from the storage electrode line; a data line crossing the gate line in an insulated manner and a drain electrode separated from the data line; and a pixel electrode coupled to the drain electrode, and the drain electrode comprises a drain bar facing the source electrode, and a drain extender overlapped with the second semiconductor layer.