Thin Film Transistor Array Panel Lithography Reduction
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Solution Overview
Problem
The manufacturing process of thin film transistor array panels is costly and time-consuming due to the multiple lithography steps required, which complicates the formation of conductive and insulating layers.
Innovation Solution
A method that simplifies the process by using a single lithography step to form data lines, drain electrodes, and semiconductor layers, and subsequently forming pixel electrodes and contact assistants using a conductive film deposited and lifted off, with photoresist layers strategically etched to expose substrate areas for direct contact, reducing the number of lithography steps needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography steps are used to form conductive and insulating layers, then manufacturing precision is improved, but manufacturing cost and time increase
Solution Approach 1:
The patent combines multiple lithography steps into a single lithography step by using a multi-layer photoresist structure. The first photoresist layer defines the pixel electrode pattern while the second photoresist layer defines the contact assistant pattern, allowing simultaneous formation of multiple conductive layers that would traditionally require separate lithography steps. This merging reduces manufacturing time while maintaining precision through the coordinated etching process.
Solution Approach 2:
The patent segments the photoresist structure into multiple layers with different functions. The first photoresist layer serves as the primary mask for pixel electrode formation, while the second photoresist layer acts as a secondary mask for contact assistant formation. This segmentation allows each layer to be optimized for its specific function while being processed together in a unified lithography step.
2Manufacturing precision
If multiple lithography steps are used to form conductive and insulating layers, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple lithography operations into a single lithography step by implementing a multi-layer photoresist system. This consolidation reduces the number of expensive lithography equipment uses, photoresist coating cycles, and alignment operations required, thereby lowering manufacturing cost while preserving the precision needed for forming complex conductive patterns including pixel electrodes and contact assistants.
Solution Approach 2:
The multi-layer photoresist structure serves multiple functions simultaneously: it defines patterns for different conductive layers, provides selective etching masks for various regions, and enables formation of both pixel electrodes and contact assistants in one process. This multi-functionality eliminates the need for separate specialized lithography steps, reducing overall manufacturing cost.
3Productivity
If the number of lithography steps is reduced, then manufacturing time and cost decrease, but manufacturing precision may be compromised
Solution Approach 1:
The patent segments the photoresist into functional layers with distinct roles. The first photoresist layer is optimized for defining pixel electrode patterns with appropriate thickness and etch resistance, while the second photoresist layer is optimized for contact assistant patterns. This segmentation ensures that each critical component receives tailored protection and definition, maintaining precision despite the reduced number of lithography steps.
Solution Approach 2:
The patent performs preliminary patterning actions by forming the multi-layer photoresist structure before the actual etching process. The photoresist layers are precisely deposited and patterned in advance to create the required mask structures, ensuring that when etching occurs, the critical components are already protected or exposed as needed, thereby maintaining high formation precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and cost by streamlining the process while ensuring accurate formation of critical components, enhancing the efficiency of thin film transistor array panel production.
Implementation Method 1
etching the passivation layer and the gate insulating layer using the first photoresist layer as a mask to expose a portion of the drain electrode and a portion of the substrate
Implementation Method 2
depositing a conductive film
Implementation Method 3
the removal of the photoresist layer may remove the first portion of the conductive film by lift off
Data Source
AI summary
A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact on the semiconductor layer; forming a data line and a drain electrode on the ohmic contact; depositing a passivation layer on the data line and the drain electrode; forming a first photoresist layer on the passivation layer; etching the passivation layer and the gate insulating layer using the first photoresist layer as a mask to expose a portion of the drain electrode and a portion of the substrate; depositing a conductive film; and removing the photoresist layer; to form a pixel electrode on a portion of the drain electrode exposed by the etching of the passivation layer.