Thin Film Transistor Array Substrate Pad Opening Process
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Solution Overview
Problem
The existing manufacturing process for thin film transistor array substrates for LCDs is complex and costly due to the requirement of a half tone mask for forming openings on the gate and data pads, leading to difficulties in mass production and conductivity issues caused by excessive residue of the patterned planarization layer.
Innovation Solution
A method that simplifies the manufacturing process by forming a patterned first metal layer with openings in the transition and pad areas, allowing a patterned planarization layer to be used as a mask for etching the second insulation layer, eliminating the need for a half tone mask and reducing production costs and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a half tone mask is used to form openings on the gate and data pads, then the insulation effect is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the half tone mask from the manufacturing process. Instead of using a half tone mask to form openings, the invention directly forms openings in the planarization insulation layer through photolithography, eliminating the need for the half tone mask and its associated complexity while maintaining the insulation effect through proper layer design and thickness control
Solution Approach 2:
The patent performs preliminary action by pre-forming the gate and data pads with appropriate openings during the initial photolithography step, before subsequent processing steps. This preliminary formation of openings eliminates the need for later mask-based modifications and simplifies the overall manufacturing process
2Reliability
If a half tone mask is used to form openings on the gate and data pads, then the insulation effect is improved, but the productivity decreases
Solution Approach 1:
The patent removes the half tone mask step from the manufacturing sequence, reducing the total number of process steps. This extraction of the unnecessary masking step directly improves productivity by enabling faster batch processing and reducing cycle time for mass production while maintaining adequate insulation through optimized layer structures
Solution Approach 2:
The patent skips the intermediate half tone mask step and proceeds directly from standard photolithography to forming the desired openings. This skipping of unnecessary process steps accelerates production throughput and improves productivity without compromising the insulation effect through proper design parameters
3Manufacturing precision
If the patterned planarization layer has excessive thickness residue, then the planarization functionality is improved, but the electrical conductivity deteriorates
Solution Approach 1:
The patent applies local quality by creating different thickness characteristics in different regions. The planarization insulation layer is designed with controlled local thickness variations, ensuring sufficient thickness in areas requiring planarization while maintaining thinner regions or openings over the gate and data pads to preserve electrical conductivity. This spatially differentiated approach resolves the contradiction between planarization quality and conductivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces production costs, and improves the yield by eliminating the need for a half tone mask, resulting in a more efficient and cost-effective method for producing thin film transistor array substrates.
Implementation Method 1
by using the planarization layer as a mask, the first insulation layer and the second insulation layer are etched to expose a portion of the drain
Data Source
AI summary
A thin film transistor array structure and a method for manufacturing the same are provided. The thin film transistor array structure comprises a substrate, including a transition area and a pad area. A patterned first metal layer is formed on the substrate, wherein the patterned first metal layer includes a data connecting line disposed in the transition area, and a data pad and a gate pad disposed in the pad area. A patterned first insulation layer is formed on the patterned first metal layer. The patterned first insulation layer at least defines a first opening on the gate pad, a second opening on the data pad, and a third opening in the transition area, so as to simplify following processes to increase the yield.