Thin Film Transistor Array Panel Etching Process
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Solution Overview
Problem
The manufacturing of thin film transistor array panels faces issues with corrosion of the source metal pattern due to reaction by-products formed during the dry-etch process, particularly when using copper, which leads to wiring defects.
Innovation Solution
A manufacturing method that uses a NF3/H2 gas-based dry-etch process to form a silicon compound on the etch surface of the data metal layer, preventing exposure and corrosion, and subsequent wet etching to form the source and drain electrodes, thereby preventing etch surface exposure and corrosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If HCl or SF6 gas is used as etching gas in the dry-etch process for forming the channel layer, then the etching process can be completed, but the etching gas reacts with the copper source metal pattern to form reaction by-products that cause wiring defects
Solution Approach 1:
The patent changes the etching gas parameters from conventional HCl or SF6 gas to a mixed gas composition containing CF4 (20-40%), C4F8 (10-30%), and O2 (30-50%). This parameter change in gas composition prevents harmful reactions with copper while maintaining effective etching performance, thereby resolving the contradiction between ease of manufacture and wiring quality
Solution Approach 2:
The patent uses a composite etching gas mixture of CF4, C4F8, and O2 instead of a single gas type. This composite gas composition provides synergistic effects where CF4 and C4F8 contribute to etching capability while O2 suppresses harmful reactions with copper, achieving both effective etching and wiring protection simultaneously
2Reliability
If the source metal pattern includes copper for low resistance, then electrical conductivity is improved, but the copper reacts with etching gas to form significant reaction by-products causing wiring defects
Solution Approach 1:
The patent modifies the etching gas composition parameters to include O2 (30-50%) which suppresses harmful reactions with copper, while maintaining CF4 and C4F8 for etching capability. This allows copper to be used for its excellent electrical conductivity without generating significant reaction by-products
Solution Approach 2:
The patent converts the potential harm of copper reactivity with etching gas into a benefit by using O2 in the gas mixture, which suppresses harmful reactions while allowing the etching process to proceed effectively, thus enabling copper's full electrical conductivity advantage to be utilized
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents corrosion of the source metal pattern and reduces wiring defects by using a NF3/H2 gas-based dry-etch process and subsequent wet etching, ensuring reliable transistor array panel production.
Implementation Method 1
a dry-etch process based on NF3 and H2 gas series is used
Implementation Method 2
in the etching of the active layer, a dry-etch process based on NF3 and H2 gas series is used
Data Source
AI summary
Provided is a manufacturing method of a thin film transistor array panel including: formation of a gate line including a gate electrode on a substrate; formation of sequentially a gate insulating layer, an active layer, a data metal layer, and a photoresist etching mask pattern on the gate line; etching the data metal layer with the same shape as the photoresist etching mask pattern; etching the active layer by using the photoresist etching mask pattern; formation of a data line including a source electrode and a drain electrode for completing a channel region on the active layer; and formation of a pixel electrode exposing the drain electrode and electrically connected with the drain electrode, in which in the etching of the active layer, a dry-etch process is performed by using gas including at least one of NF3 and H2.