TFT Array Panel Photolithography Reduction
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Solution Overview
Problem
The manufacturing of thin film transistor (TFT) array panels for active matrix display devices, such as LCDs and OLEDs, is hindered by the high cost and time associated with repeated photolithography steps, necessitating a reduction in these processes to enhance efficiency and reduce costs.
Innovation Solution
The TFT array panel design and manufacturing method involve forming a substrate with data and gate electrodes, semiconductor layers, and passivation layers, utilizing a reduced number of photolithography steps to create contact holes and connectors, allowing for the integration of pixel electrodes and signal lines with fewer processing stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and etching steps are used repeatedly to pattern multiple thin film layers, then the TFT array panel can be manufactured with precise patterns, but the manufacturing cost and time increase
Solution Approach 1:
The patent combines multiple photolithography and etching steps into a single integrated process. Specifically, a multi-layer conductive structure is formed using one photolithography step that patterns all conductive layers simultaneously, followed by a single etching step that removes excess material from all layers at once. This merging of steps maintains pattern precision while dramatically reducing manufacturing time and cost.
Solution Approach 2:
The patent segments the manufacturing process by forming the multi-layer conductive structure as an integrated unit rather than patterning each layer separately. The conductive layers are deposited in sequence and then processed together through a unified photolithography and etching sequence, creating distinct functional segments (data lines, gate lines, pixel electrodes) within a single process flow.
2Manufacturing precision
If photolithography and etching steps are used repeatedly to pattern multiple thin film layers, then the TFT array panel can be manufactured with precise patterns, but the manufacturing cost increases
Solution Approach 1:
The patent merges multiple photolithography and etching operations into a single integrated process sequence. By forming all conductive layers and patterning them in one unified workflow rather than processing each layer independently, the manufacturing cost is reduced while maintaining the necessary pattern precision for functional TFT operation.
3Loss of time
If a reduced number of photolithography steps is used, then manufacturing cost and time decrease, but the complexity of forming multiple thin film layers increases
Solution Approach 1:
The patent applies preliminary action by depositing multiple conductive layers in a predetermined sequence before performing the single photolithography and etching step. The layers are prepared in advance with correct materials and thicknesses, so that when the unified patterning process occurs, all layers are ready to be patterned simultaneously without requiring complex in-process adjustments.
Data Source
AI summary
A thin film transistor array panel includes a substrate, a data line and a gate electrode formed on the substrate, a insulating layer formed on the data line and the gate electrode, a semiconductor layer formed on the insulating layer, a drain electrode and a source electrode formed on the semiconductor layer, a passivation layer formed on the drain electrode and the source electrode including a first contact hole to expose a portion of the data line, a second contact hole to expose a portion of the source electrode, a third contact hole to expose a portion of the drain electrode, and a fourth contact hole to expose a portion of gate electrode, a first connector formed on the passivation layer and connected to the data line and the source electrode through the first contact hole and the second contact hole, a gate line formed on the passivation layer and connected to the gate electrode through the fourth contact hole, and a pixel electrode connected to the drain electrode through the third contact hole.