Thin Film Transistor Array Panel Single Mask Etching

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Solution Overview

Problem

The manufacturing process of thin film transistor array panels for LCDs is costly and time-consuming due to the need for multiple masks, and the etching of metal and semiconductor layers using the same mask results in afterimages and semiconductor pollution from light leakage.

Innovation Solution

The use of a photoresist pattern with a controlled flow ratio of chlorine-containing and fluorine-containing gases during etching prevents diffusion of Mo into semiconductors and splitting of impurities from the Al film, allowing for the same mask to be used for both metal and semiconductor etching without leaving afterimages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If separate masks are used for metal layer etching and semiconductor layer etching, then etching precision is improved and semiconductor pollution is prevented, but manufacturing cost increases and production time is extended

Engineering Contradiction:
Improveetching precisionVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent combines the etching processes for metal layers and semiconductor layers into a single step using one mask. The photoresist pattern serves as a unified mask that defines both metal patterns and semiconductor patterns simultaneously, eliminating the need for separate masking and etching operations. This merging of processes reduces manufacturing steps, lowers costs, and improves productivity while maintaining pattern alignment through the single mask approach.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If the same mask is used for metal layer etching and semiconductor layer etching, then manufacturing efficiency is improved and the number of masks is reduced, but semiconductor pollution occurs and afterimages are generated

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidsemiconductor pollution
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and removes the harmful elements (metal particles and impurities) from the semiconductor layer immediately after the combined etching process. A cleansing step is introduced that specifically targets and removes metal particles and other contaminants from the semiconductor surface, eliminating the pollution problem caused by using the same mask for both etching operations while maintaining the efficiency benefits of the single-mask approach.

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If the same mask is used for metal layer etching and semiconductor layer etching, then the number of masks is reduced, but light leakage causes afterimages

Engineering Contradiction:
Improvenumber of masksVSAvoidafterimages
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful effect of light leakage during etching into a beneficial outcome. The light exposure that would normally cause unwanted semiconductor formation is utilized to create a photoresist pattern that precisely defines the desired patterns. The photoresist material transforms the potentially harmful light exposure into a controlled patterning mechanism, where the light-exposed areas become the precise boundaries for both metal and semiconductor patterns, eliminating afterimages while maintaining single-mask simplicity.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the number of masks required, improves TFT characteristics by minimizing semiconductor pollution and afterimage occurrence, and enhances the manufacturing efficiency of thin film transistor array panels.

Implementation Method 1

the Al film and the underlying Mo film are wet-etched

Methodology Applied
Scientific EffectChemical etching:

Implementation Method 2

a plasma process is used to remove organic material from the channel area

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS8173493B2Thin film transistor array panel and fabrication
Publication Date: 2012.05.08 SAMSUNG DISPLAY CO LTD
  • US8173493B2 patent drawing
  • US8173493B2 patent drawing
  • US8173493B2 patent drawing

AI summary

The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.